EDS2508APSA Datasheet, PDF (1/51 Pages) Elpida Memory – 256M bits SDRAM

DATA SHEET
256M bits SDRAM
EDS2508APSA (32M words × 8 bits)
EDS2516APSA (16M words × 16 bits)
Description
The EDS2508AP is a 256M bits SDRAM organized as
8,388,608 words × 8 bits × 4 banks. The EDS2516AP
is a 256M bits SDRAM organized as 4194304 words ×
16 bits × 4 banks. All inputs and outputs are referred to
the rising edge of the clock input. It is packaged in
standard 60-ball µBGA^.
Features
• 3.3V power supply
• Clock frequency: 133MHz (max.)
• LVTTL interface
• Single pulsed /RAS
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
 Sequential (BL = 1, 2, 4, 8)
 Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
: DQM (EDS2508AP)
: UDQM, LDQM (EDS2516AP)
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
 Auto refresh
 Self refresh
Pin Configurations
/xxx indicates active low signal.
123456
A
VSS DQ15
(DQ7)*
B
DQ14 VSSQ
(NC)*
C
DQ13 VDDQ
(DQ6)*
D
DQ12 DQ11
(NC)* (DQ5)*
E
DQ10 VSSQ
(NC)*
F
DQ9 VDDQ
(DQ4)*
G
DQ8 NC
(NC)*
H
NC VSS
J
NC UDQM
(DQM)*
K
NC CLK
L
CKE A12
M
A11 A9
N
A8 A7
P
A6 A5
R
VSS A4
DQ0 VDD
VDDQ DQ1
(NC)*
VSSQ DQ2
(DQ1)*
DQ4 DQ3
(DQ2)* (NC)*
VDDQ DQ5
(NC)*
VSSQ DQ6
(DQ3)*
NC DQ7
(NC)*
VDD NC
LDQM /WE
(NC)*
/RAS /CAS
NC /CS
BA1 BA0
A0 A10
A2 A1
A3 VDD
(Top view)
Note: ( )* marked pins are for EDS2508APSA.
A0 to A12, Address input
BA0, BA1 Bank select address
DQ0 to DQ15 Data-input/output
/CS
Chip select
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write enable
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0228E30 (Ver. 3.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc.2001-2002