EDS2508ADTA Datasheet, PDF (1/50 Pages) Elpida Memory – 256M bits SDRAM

PRELIMINARY DATA SHEET
256M bits SDRAM
EDS2508ADTA (32M words × 8 bits) _Description
The EDS2508ADTA is 256M bits SDRAMs organized
as 8,388,608 words × 8 bits × 4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
EThey are packaged in 54-pin plastic TSOP (II).
Features
• 3.3V power supply
O_{• Clock frequency: 133MHz (max.)}
• Single pulsed /RAS
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
L _{write operation capability}
• 2 variations of burst sequence
 Sequential (BL = 1, 2, 4, 8, full page)
 Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
P ^{• Byte control by DQM}
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
 Auto refresh
r ^{ Self refresh}
oduct ^{• TSOP (II) package with lead free solder (Sn-Bi)}
Pin Configurations
/xxx indicate active low signal.
54-pin Plastic TSOP (II)
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
54
2
53
3
52
4
51
5
50
6
49
7
48
8
47
9
46
10
45
11
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
(Top view)
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
A0 to A12
BA0, BA1
DQ0 to DQ7
/CS
/RAS
/CAS
/WE
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0633E10 (Ver. 1.0) _{This product became EOL in September, 2007.}
Date Published January 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005