EDS2504ACTA Datasheet, PDF (1/51 Pages) Elpida Memory – 256M bits SDRAM

DATA SHEET
256M bits SDRAM
EDS2504ACTA, EDS2504APTA (64M words × 4 bits)
EDS2508ACTA, EDS2508APTA (32M words × 8 bits)
EDS2516ACTA, EDS2516APTA (16M words × 16 bits)
Description
Pin Configurations
The EDS2504AC/AP is a 256M bits SDRAM organized
as 16,777,216 words × 4 bits × 4 banks. The EDS2508
AC/AP is a 256M bits SDRAM organized as 8,388,608
words × 8 bits × 4 banks. The EDS2516 AC/AP is a
256M bits SDRAM organized as 4194304 words × 16
bits × 4 banks. All inputs and outputs are referred to
the rising edge of the clock input. It is packaged in
standard 54-pin plastic TSOP (II).
Features
• 3.3V power supply
• Clock frequency: 133MHz (max.)
• LVTTL interface
• Single pulsed /RAS
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length* (BL): 1, 2, 4, 8
• 2 variations of burst sequence
 Sequential (BL = 1, 2, 4, 8)
 Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
: DQM (EDS2504AC/AP, EDS2508AC/AP)
: UDQM, LDQM (EDS2516AC/AP)
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
 Auto refresh
 Self refresh
Note: EDS2504AP/08AP/16AP is supported full page
function.
/xxx indicates active low signal.
Index
Index
EDS2504AC/08AC/16AC
EDS2504AP/08AP/16AP
54-pin TSOP
VDD VDD VDD 1
NC DQ0 DQ0 2
VDDQ VDDQ VDDQ 3
NC NC DQ1 4
DQ0 DQ1 DQ2 5
VSSQ VSSQ VSSQ 6
NC NC DQ3 7
NC DQ2 DQ4 8
VDDQ VDDQ VDDQ 9
NC NC DQ5 10
DQ1 DQ3 DQ6 11
VSSQ VSSQ VSSQ 12
NC NC DQ7 13
VDD VDD VDD 14
NC NC LDQM 15
/WE /WE /WE 16
/CAS /CAS /CAS 17
/RAS /RAS /RAS 18
/CS /CS /CS 19
BA0 BA0 BA0 20
BA1 BA1 BA1 21
A10 A10 A10 22
A0 A0 A0 23
A1 A1 A1 24
A2 A2 A2 25
A3 A3 A3 26
VDD VDD VDD 27
54 VSS VSS VSS
53 DQ15 DQ7 NC
52 VSSQ VSSQ VSSQ
51 DQ14 NC NC
50 DQ13 DQ6 DQ3
49 VDDQ VDDQ VDDQ
48 DQ12 NC NC
47 DQ11 DQ5 NC
46 VSSQ VSSQ VSSQ
45 DQ10 NC NC
44 DQ9 DQ4 DQ2
43 VDDQ VDDQ VDDQ
42 DQ8 NC NC
41 VSS VSS VSS
40 NC NC NC
39 UDQM DQM DQM
38 CLK CLK CLK
37 CKE CKE CKE
36 A12 A12 A12
35 A11 A11 A11
34 A9 A9 A9
33 A8 A8 A8
32 A7 A7 A7
31 A6 A6 A6
30 A5 A5 A5
29 A4 A4 A4
28 VSS VSS VSS
X 16
X8
X4
(Top view)
A0 to A12, Address input
BA0, BA1 Bank select address
DQ0 to DQ15 Data-input/output
/CS
Chip select
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write enable
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0110E30 (Ver. 3.0)
Date Published November 2001 (K) Japan
URL: http://www.elpida.com
C Elpida Memory, Inc. 2001