EDS1616GGBH Datasheet, PDF (1/49 Pages) Elpida Memory – 16M bits SDRAM

PRELIMINARY DATA SHEET
16M bits SDRAM
EDS1616GGBH (1M words × 16 bits) _{Specifications}
• Density: 16M bits
• Organization
⎯ 512K words × 16 bits × 2 banks
E• Package: 60-ball FBGA
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 3.3V ± 0.3V
• Clock frequency: 100MHz (max.)
O• Two internal banks for concurrent operation
• Interface: LVTTL
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
L ^{⎯ Sequential (1, 2, 4, 8, full page)}
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA
1
2
3
4
5
A
VSS DQ15
B
DQ14 VSSQ
C
DQ13 VDDQ
D
DQ12 DQ11
6
7
DQ0 VDD
VDDQ DQ1
VSSQ DQ2
DQ4 DQ3
⎯ Interleave (1, 2, 4, 8)
• /CAS Latency (CL): 2, 3
• Precharge: auto precharge operation for each burst
access
• Refresh: auto-refresh, self-refresh
P ^{• Refresh cycles: 2048 cycles/32ms}
⎯ Average refresh period: 15.6μs
• Operating ambient temperature range
⎯ TA = 0°C to +70°C
r _Features
• Single pulsed /RAS
o • Burst read/write operation and burst read/single write
operation capability
• Byte control by UDQM and LDQM
duct ^{• tDPL = 1CLK}
E
DQ10 VSSQ
F
DQ9 VDDQ
G
DQ8 NC
H
NC NC
J
NC UDQM
K
NC CLK
L
CKE NC
M
BA A9
N
A8 A7
P
A6 A5
R
VSS A4
VDDQ DQ5
VSSQ DQ6
NC DQ7
NC NC
LDQM /WE
/RAS /CAS
NC /CS
NC NC
A0 A10
A2 A1
A3 VDD
(Top view)
A0 to A10
BA
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0682E20 (Ver. 2.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2005