EDS1616AGTA Datasheet, PDF (1/49 Pages) Elpida Memory – 16M bits SDRAM (1M words x 16 bits)

DATA SHEET
16M bits SDRAM
EDS1616AGTA (1M words × 16 bits)
Description
Pin Configurations
The EDS1616AGTA is 16M bits SDRAM organized as
524,288 words × 16 bits × 2 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 50-pin plastic TSOP (II).
Features
• 3.3V power supply
• Clock frequency: 166MHz/133MHz (max.)
• Single pulsed /RAS
• ×16 organization
• 2 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• Programmable burst length (BL): 1, 2, 4, 8 and full
page
• 2 variations of burst sequence
 Sequential (BL = 1, 2, 4, 8, full page)
 Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by UDQM and LDQM
• Refresh cycles: 2048 refresh cycles/32ms
• 2 variations of refresh
 Auto refresh
 Self refresh
• TSOP (II) package with lead free solder (Sn-Bi)
/xxx indicate active low signal.
50-pin Plastic TSOP (II)
VDD ¹
50
DQ0 ²
49
DQ1 ³
48
VSSQ ⁴
47
DQ2 ⁵
46
DQ3 ⁶
45
VDDQ ⁷
44
DQ4 ⁸
43
DQ5 ⁹
42
VSSQ ¹⁰
41
DQ6 ¹¹
40
DQ7 ¹²
39
VDDQ ¹³
38
LDQM ¹⁴
37
/WE ¹⁵
36
/CAS ¹⁶
35
/RAS ¹⁷
34
/CS ¹⁸
33
BA ¹⁹
32
A10 ²⁰
31
A0 ²¹
30
A1 ²²
29
A2 ²³
28
A3 ²⁴
27
VDD ²⁵
26
(Top view)
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
A0 to A10
BA
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0504E40 (Ver. 4.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005