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EDS1232CABB Datasheet, PDF (1/55 Pages) Elpida Memory – 128M bits SDRAM | |||
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PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1232CABB, EDS1232CATA (4M words à 32 bits)
Description
The EDS1232CA is a 128M bits SDRAM organized as
1,048,576 words à 32 bits à 4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
They are packaged in 90-ball FBGA, 86-pin plastic
TSOP (II).
Features
⢠2.5V power supply
⢠Clock frequency: 133MHz (max.)
⢠Single pulsed /RAS
⢠Ã32 organization
⢠4 banks can operate simultaneously and
independently
⢠Burst read/write operation and burst read/single write
operation capability
⢠Programmable burst length (BL): 1, 2, 4, 8 and full
page
⢠2 variations of burst sequence
 Sequential (BL = 1, 2, 4, 8)
 Interleave (BL = 1, 2, 4, 8)
⢠Programmable /CAS latency (CL): 2, 3
⢠Byte control by DQM
⢠Refresh cycles: 4096 refresh cycles/64ms
⢠2 variations of refresh
 Auto refresh
 Self refresh
⢠FBGA package is lead free solder (Sn-Ag-Cu)
Document No. E0247E40 (Ver. 4.0)
Date Published July 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
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