EDS1216AGTA Datasheet, PDF (1/49 Pages) Elpida Memory – 128M bits SDRAM (8M words × 16 bits)

PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1216AGTA (8M words × 16 bits)
Specifications
• Density: 128M bits
• Organization
 2M words × 16 bits × 4 banks
• Package: 54-pin plastic TSOP (II)
 Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 3.3V ± 0.3V
• Clock frequency: 166MHz/133MHz (max.)
• Four internal banks for concurrent operation
• Interface: LVTTL
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
 Sequential (1, 2, 4, 8, full page)
 Interleave (1, 2, 4, 8)
• /CAS Latency (CL): 2, 3
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
 Average refresh period: 15.6µs
• Operating ambient temperature range
 TA = 0°C to +70°C
Features
• Single pulsed /RAS
• Burst read/write operation and burst read/single write
operation capability
• Byte control by UDQM and LDQM
Pin Configurations
/xxx indicates active low signal.
54-pin Plastic TSOP (II)
VDD ¹
54
DQ0 ²
53
VDDQ
3
52
DQ1 ⁴
51
DQ2 ⁵
50
VSSQ
6
49
DQ3 ⁷
48
DQ4 ⁸
47
VDDQ
9
46
DQ5 ¹⁰
45
DQ6 ¹¹
44
VSSQ
12
43
DQ7 ¹³
42
VDD ¹⁴
41
LDQM ¹⁵
40
/WE ¹⁶
39
/CAS ¹⁷
38
/RAS ¹⁸
37
/CS ¹⁹
36
BA0 ²⁰
35
BA1 ²¹
34
A10 ²²
33
A0 ²³
32
A1 ²⁴
31
A2 ²⁵
30
A3 ²⁶
29
VDD ²⁷
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0847E20 (Ver. 2.0)
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005-2006