EDS1216AABH Datasheet, PDF (1/49 Pages) Elpida Memory – 128M bits SDRAM (8M words x 16 bits)

DATA SHEET
128M bits SDRAM
EDS1216AABH, EDS1216CABH
(8M words × 16 bits)
Description
Pin Configurations
The EDS1216AABH, EDS1216CABH are 128M bits
SDRAM organized as 2,097,152 words × 16 bits × 4
banks. All inputs and outputs are synchronized with
the positive edge of the clock.
Supply voltages are 3.3V (EDS1216AABH) and 2.5V
(EDS1216CABH).
They are packaged in 54-ball FBGA.
Features
• 3.3V and 2.5V power supply
• Clock frequency: 133MHz (max.)
• Single pulsed /RAS
• ×16 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
 Sequential (BL = 1, 2, 4, 8, full page)
 Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by UDQM and LDQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
 Auto refresh
 Self refresh
• FBGA package with lead free solder (Sn-Ag-Cu)
/xxx indicate active low signal.
54-ball FBGA
123456789
A
VSS DQ15 VSSQ
B
DQ14 DQ13 VDDQ
C
DQ12 DQ11 VSSQ
D
DQ10 DQ9 VDDQ
E
DQ8 NC VSS
F
UDQM CLK CKE
G
NC A11 A9
H
A8 A7 A6
J
VSS A5 A4
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD LDQM DQ7
/CAS /RAS /WE
BA0 BA1 /CS
A0 A1 A10
A3 A2 VDD
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
/CS
/RAS
/CAS
/WE
LDQM /UDQM
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select
Data inputs/ outputs
Clock input
Clock enable
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Power supply
Ground
Power supply for DQ
Ground for DQ
No connection
Document No. E0410E40 (Ver. 4.0)
Date Published February 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2005