EDE5108ABSE-BE Datasheet, PDF (1/65 Pages) Elpida Memory – 512M bits DDR2 SDRAM for HYPER DIMM

PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
for HYPER DIMM
EDE5108ABSE-BE, -AE (64M words × 8 bits) _Description
The EDE5108AB is a 512M bits DDR2 SDRAM
E^{organized as 16,777,216 words × 8 bits × 4 banks.}
OL ^{It is packaged in 64-ball FBGA package.}
Features
• 1.8V power supply
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• Burst lengths: 4, 8
P • /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• 7.8µs average periodic refresh interval
r ^{• 1.8V (SSTL_18 compatible) I/O}
• Posted CAS by programmable additive latency for
better command and data bus efficiency
o• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
d• /DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
• FBGA package with lead free solder
uct ^(Sn-Ag-Cu)
Document No. E0540E11 (Ver. 1.1) _{This Product became EOL in October, 2006.}
Date Published February 2006 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2006