EDE5104AHSE Datasheet, PDF (1/69 Pages) Elpida Memory – 512M bits DDR2 SDRAM

PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5104AHSE (128M words × 4 bits)
Specifications
• Density: 512M bits
• Organization
⎯ 32M words × 4 bits × 4 banks
• Package
⎯ 60-ball FBGA
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate: 667Mbps (max.)
• 1KB page size
⎯ Row address: A0 to A13
⎯ Column address: A0 to A9, A11
• Four internal banks for concurrent operation
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• Burst type (BT):
⎯ Sequential (4, 8)
⎯ Interleave (4, 8)
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst
access
• Driver strength: normal/weak
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
⎯ Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
⎯ TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E0999E10 (Ver. 1.0)
Date Published December 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2006