EDD51321CBH Datasheet, PDF (1/55 Pages) Elpida Memory – 512M bits DDR SDRAM

PRELIMINARY DATA SHEET
512M bits DDR SDRAM
EDD51321CBH (16M words × 32 bits)
Specifications
• Density: 512M bits
• Organization
⎯ × 32 bits: 4M words × 32 bits × 4 banks
• Package: 90-ball FBGA
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 1.8V +0.15V/–0.1V
• Clock frequency: 166MHz/133MHz (max.)
• 2KB page size
⎯ Row address: A0 to A12
⎯ Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVCMOS
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
⎯ Sequential (2, 4, 8)
⎯ Interleave (2, 4, 8)
• /CAS Latency (CL): 3
• Precharge: auto precharge option for each burst
access
• Driver strength: full/half/quarter
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
⎯ Average refresh period: 7.8μs
• Operating ambient temperature range
⎯ TA = −20°C to +85°C
Features
• DLL is not implemented
• Low power consumption
• Double-data-rate architecture; two data transfers per
one clock cycle
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver.
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Burst termination by burst stop command and
Precharge command
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA
123456789
A
VSS DQ31 VSSQ
B
VDDQ DQ29 DQ30
C
VSSQ DQ27 DQ28
D
VDDQ DQ25 DQ26
E
VSSQ DQS3 DQ24
F
VDD DM3 NC
G
CKE CK /CK
H
A9 A11 A12
J
A6 A7 A8
K
A4 DM1 A5
L
VSSQ DQS1 DQ8
M
VDDQ DQ9 DQ10
N
VSSQ DQ11 DQ12
P
VDDQ DQ13 DQ14
R
VSS DQ15 VSSQ
VDDQ DQ16 VDD
DQ17 DQ18 VSSQ
DQ19 DQ20 VDDQ
DQ21 DQ22 VSSQ
DQ23 DQS2 VDDQ
NC DM2 VSS
/WE /CAS /RAS
/CS BA0 BA1
A10 (AP) A0 A1
A2 DM0 A3
DQ7 DQS0 VDDQ
DQ5 DQ6 VSSQ
DQ3 DQ4 VDDQ
DQ1 DQ2 VSSQ
VDDQ DQ0 VDD
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ31
DQS0 to DQS3
/CS
/RAS
/CAS
/WE
DM0 to DM3
CKE
CK
/CK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe
Column address strobe
Write enable
Input mask
Clock enable
Clock input
Differential clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E1094E30 (Ver. 3.0)
Date Published November 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2007