EDD5116ADTA-5CLI-E Datasheet, PDF (1/48 Pages) Elpida Memory – 512M bits DDR SDRAM WTR (Wide Temperature Range)

DATA SHEET
512M bits DDR SDRAM
WTR (Wide Temperature Range)
EDD5116ADTA-5CLI-E (32M words × 16 bits, DDR400) _Description
The EDD5116AD is 512M bits Double Data Rate
E(DDR) SDRAM, organized as 8,388,608 words × 16
bits × 4 banks.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2 bits prefetch-pipelined
Oarchitecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
L ^{It is packaged in 66-pin plastic TSOP (II).}
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
Features
• Power supply: VDD, VDDQ = 2.6V ± 0.1V
• Data rate: 400Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
P • Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
r ^{• 4 internal banks for concurrent operation}
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
o _{• Differential clock inputs (CK and /CK)}
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
d and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
u _{• Programmable burst length (BL): 2, 4, 8}
• Programmable /CAS latency (CL): 3
• Programmable output driver strength: normal/weak
c ^{• Refresh cycles: 8192 refresh cycles/64ms}
 7.8µs maximum average periodic refresh interval
• 2 variations of refresh
t ^{ Auto refresh}
VSSQ 12
DQ7 13
NC 14
VDDQ 15
LDQS 16
NC 17
VDD 18
NC 19
LDM 20
/WE 21
/CAS 22
/RAS 23
/CS 24
NC 25
BA0 26
BA1 27
A10(AP) 28
A0 29
A1 30
A2 31
A3 32
VDD 33
55 VDDQ
54 DQ8
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 /CK
45 CK
44 CKE
43 NC
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
A0 to A12
BA0, BA1
DQ0 to DQ15
LDQS, UDQS
/CS
/RAS
/CAS
/WE
LDM, UDM
CK
/CK
CKE
VREF
VDD
(Top view)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
 Self refresh
• Ambient temperature range: –40 to +85°C
VSS
VDDQ
VSSQ
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
• TSOP package with lead free solder (Sn-Bi)
NC
No connection
Document No. E0563E10 (Ver. 1.0) _{This product became EOL in September, 2007.}
Date Published July 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004