EDD5108AFTA Datasheet, PDF (1/49 Pages) Elpida Memory – 512M bits DDR SDRAM

DATA SHEET
512M bits DDR SDRAM
EDD5108AFTA (64M words × 8 bits)
EDD5116AFTA (32M words × 16 bits)
Description
The EDD5108AFTA and the EDD5116AFTA are 512M
bits Double Data Rate (DDR) SDRAM organized as
16,777,216 words × 8 bits × 4 banks and 8,388,608
words × 16 bits × 4 banks, respectively. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. It is
packaged in standard 66-pin plastic TSOP (II).
Features
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Data Rate: 333Mbps/266Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Programmable output driver strength: normal/weak
• Refresh cycles: 8192 refresh cycles/64ms
 7.8µs maximum average periodic refresh interval
• 2 variations of refresh
 Auto refresh
 Self refresh
• TSOP (II) package with lead free solder (Sn-Bi)
 RoHS compliant
Pin Configurations
/xxx indicates active low signal.
VDD VDD
DQ0 DQ0
VDDQ VDDQ
NC DQ1
DQ1 DQ2
VSSQ VSSQ
NC DQ3
DQ2 DQ4
VDDQ VDDQ
NC DQ5
DQ3 DQ6
VSSQ VSSQ
NC DQ7
NC NC
VDDQ VDDQ
NC LDQS
NC NC
VDD VDD
NC NC
NC LDM
/WE /WE
/CAS /CAS
/RAS /RAS
/CS /CS
NC NC
BA0 BA0
BA1 BA1
A10(AP) A10(AP)
A0
A0
A1
A1
A2
A2
A3
A3
VDD VDD
66-pin plastic TSOP(II)
1
66
2
65
3
64
4
63
5
62
6
61
7
60
8
59
9
58
10
57
11
56
12
55
13
54
14
53
15
52
16
51
17
50
18
49
19
48
20
47
21
46
22
45
23
44
24
43
25
42
26
41
27
40
28
39
29
38
30
37
31
36
32
35
33
34
VSS VSS
DQ15 DQ7
VSSQ VSSQ
DQ14 NC
DQ13 DQ6
VDDQ VDDQ
DQ12 NC
DQ11 DQ5
VSSQ VSSQ
DQ10 NC
DQ9 DQ4
VDDQ VDDQ
DQ8 NC
NC NC
VSSQ VSSQ
UDQS DQS
NC NC
VREF VREF
VSS VSS
UDM DM
/CK /CK
CK CK
CKE CKE
NC NC
A12 A12
A11 A11
A9 A9
A8 A8
A7 A7
A6 A6
A5 A5
A4 A4
VSS VSS
X 16
X8
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, UDQS, LDQS
/CS
/RAS
/CAS
/WE
DM, UDM, LDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
(Top view)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0699E20 (Ver. 2.0)
Date Published October 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005