EDD5108AFBG Datasheet, PDF (1/52 Pages) Elpida Memory – 512M bits DDR SDRAM

PRELIMINARY DATA SHEET
512M bits DDR SDRAM
EEDDDD55111068AAFFBBGG((3624MMwwoorrddss××186bbititss)) _{Specifications}
• Density: 512M bits
• Organization
E 16M words × 8 bits × 4 banks (EDD5108AFBG)
 8M words × 16 bits × 4 banks (EDD5116AFBG)
• Package: 60-ball FBGA
 Lead-free (RoHS compliant)
O_{• Power supply:}
 DDR400: VDD, VDDQ = 2.6V ± 0.1V
 DDR333: VDD, VDDQ = 2.5V ± 0.2V
L ^{• Data rate: 400Mbps/333Mbps (max.)}
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
 Sequential (2, 4, 8)
 Interleave (2, 4, 8)
P _{• /CAS Latency (CL): 2, 2.5, 3}
• Precharge: auto precharge option for each burst
access
• Driver strength: normal/weak
r _{• Refresh: auto-refresh, self-refresh}
• Refresh cycles: 8192 cycles/64ms
o ^{ Average refresh period: 7.8µs}
• Operating ambient temperature range
duct ^{ TA = 0°C to +70°C}
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
Document No. E0887E20 (Ver. 2.0)
Date Published November 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in April, 2010.
Elpida Memory, Inc. 2006