EDD5108ADTA-TI Datasheet, PDF (1/49 Pages) Elpida Memory – 512M bits DDR SDRAM WTR (Wide Temperature Range)

PRELIMINARY DATA SHEET
512M bits DDR SDRAM
WTR (Wide Temperature Range)
EEDDDD55111068AADDTTAA--TTII((3624MMwwoorrddss××186bbititss)) _Description
EThe the EDD5108AD and the EDD5116AD are 512M
bits Double Data Rate (DDR) SDRAM. Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 2 bits prefetch-pipelined architecture. Data
O_{strobe (DQS) both for read and write are available for}
high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
L ^{Loop (DLL) can be set enable or disable.}
Pin Configurations
/xxx indicates active low signal.
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
66-pin Plastic TSOP(II)
1
66
2
65
3
64
4
63
5
62
6
61
7
60
8
59
9
58
10
57
VSS VSS
DQ15 DQ7
VSSQ VSSQ
DQ14 NC
DQ13 DQ6
VDDQ VDDQ
DQ12 NC
DQ11 DQ5
VSSQ VSSQ
DQ10 NC
Features
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Data Rate: 333Mbps/266Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
P _{/received with data, to be used in capturing data at}
the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
r ^{• 4 internal banks for concurrent operation}
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
o _{• Differential clock inputs (CK and /CK)}
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
d _{and data mask referenced to both edges of DQS}
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
u _{• Programmable burst length (BL): 2, 4, 8}
• Programmable /CAS latency (CL): 2, 2.5
• Programmable output driver strength: normal/weak
c ^{• Refresh cycles: 8192 refresh cycles/64ms}
 7.8µs maximum average periodic refresh interval
• 2 variations of refresh
t ^{ Auto refresh}
DQ3 DQ6 11
VSSQ VSSQ 12
NC DQ7 13
NC NC 14
VDDQ VDDQ 15
NC LDQS 16
NC NC 17
VDD VDD 18
NC NC 19
NC LDM 20
/WE /WE 21
/CAS /CAS 22
/RAS /RAS 23
/CS /CS 24
NC NC 25
BA0 BA0 26
BA1 BA1 27
A10(AP) A10(AP) 28
A0
A0 29
A1
A1 30
A2
A2 31
A3
A3 32
VDD VDD 33
X 16
X8
56 DQ9 DQ4
55 VDDQ VDDQ
54 DQ8 NC
53 NC NC
52 VSSQ VSSQ
51 UDQS DQS
50 NC NC
49 VREF VREF
48 VSS VSS
47 UDM DM
46 /CK /CK
45 CK CK
44 CKE CKE
43 NC NC
42 A12 A12
41 A11 A11
40 A9 A9
39 A8 A8
38 A7 A7
37 A6 A6
36 A5 A5
35 A4 A4
34 VSS VSS
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, LDQS, UDQS
/CS
/RAS
/CAS
/WE
DM, LDM, UDM
CK
/CK
CKE
VREF
VDD
(Top view)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
VSS
Ground for internal circuit
 Self refresh
VDDQ
Power for DQ circuit
• Ambient temperature range: −40 to +85°C
VSSQ
NC
Ground for DQ circuit
No connection
Document No. E0438E10 (Ver. 1.0) _{This product became EOL in September, 2007.}
Date Published November 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003