EDD2516KCTA-SI Datasheet, PDF (1/52 Pages) Elpida Memory – 256M bits DDR SDRAM 256M bits DDR SDRAM

PRELIMINARY DATA SHEET
256M bits DDR SDRAM
with Super Self-Refresh
EDD2516KCTA-SI (16M words × 16 bits) _{Specifications}
• Density: 256M bits
E• Organization
⎯ 4M words × 16 bits × 4 banks
• Package: 66-pin plastic TSOP (II)
⎯ Lead-free (RoHS compliant)
O^{• Power supply: VDD, VDDQ = 2.5V ± 0.2V}
• Data rate: 333Mbps/266Mbps (max.)
• Four internal banks for concurrent operation
• Interface: SSTL_2
L ^{• Burst lengths (BL): 2, 4, 8}
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
VSSQ 12
DQ7 13
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
55 VDDQ
54 DQ8
• Burst type (BT):
⎯ Sequential (2, 4, 8)
⎯ Interleave (2, 4, 8)
• /CAS Latency (CL): 2, 2.5
• Precharge: auto precharge operation for each burst
access
P _{• Driver strength: normal/weak}
• Refresh: auto-refresh, super self-refresh with Auto
Temperature Compensated Self-refresh (ATCSR)
function
r _{• Refresh cycles: 8192 cycles/64ms}
⎯ Average refresh period: 7.8μs
o ^{• Operating ambient temperature range}
⎯ TA = −40°C to +85°C
Features
d • Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
u • Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
c ^{• Differential clock inputs (CK and /CK)}
• DLL aligns DQ and DQS transitions with CK
transitions
t ^{• Commands entered on each positive CK edge; data}
NC 14
VDDQ 15
LDQS 16
SF 17
VDD 18
NC 19
LDM 20
/WE 21
/CAS 22
/RAS 23
/CS 24
NC 25
BA0 26
BA1 27
A10(AP) 28
A0 29
A1 30
A2 31
A3 32
VDD 33
(Top view)
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 /CK
45 CK
44 CKE
43 NC
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
A0 to A12
BA0, BA1
DQ0 to DQ15
UDQS/LDQS
/CS
/RAS
/CAS
/WE
UDM/LDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
SF
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
SSR Flag
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• SSR Flag function available
Document No. E0555E40 (Ver.4.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in April, 2007.
©Elpida Memory, Inc. 2004-2005