EDD2516AKTA-5CLI Datasheet, PDF (1/48 Pages) Elpida Memory – 256M bits DDR SDRAM WTR (Wide Temperature Range)

PRELIMINARY DATA SHEET
256M bits DDR SDRAM
WTR (Wide Temperature Range)
EDD2516AKTA-5CLI (16M words × 16 bits, DDR400) _Description
The EDD2516AKTA-5 is a 256M bits DDR SDRAM
organized as 4,194,304 words × 16 bits × 4 banks.
ERead and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
O^{write are available for high speed and reliable data bus}
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in standard 66-pin plastic TSOP (II).
L ^Features
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
• Power supply: VDDQ = 2.6V ± 0.1V
: VDD = 2.6V ± 0.1V
• Data rate: 400Mbps (max.)
• Double Data Rate architecture; two data transfers
per clock cycle
P • Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
r _{• 4 internal banks for concurrent operation}
• DQS is edge aligned with data for READs; center
o ^{aligned with data for WRITEs}
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
d • Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
u • SSTL_2 compatible I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 3
• Programmable output driver strength: normal/weak
c _{• Refresh cycles: 8192 refresh cycles/64ms}
⎯ 7.8μs maximum average periodic refresh interval
t ^{• 2 variations of refresh}
VSSQ 12
DQ7 13
NC 14
VDDQ 15
LDQS 16
NC 17
VDD 18
NC 19
LDM 20
/WE 21
/CAS 22
/RAS 23
/CS 24
NC 25
BA0 26
BA1 27
A10(AP) 28
A0 29
A1 30
A2 31
A3 32
VDD 33
(Top view)
55 VDDQ
54 DQ8
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 /CK
45 CK
44 CKE
43 NC
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
A0 to A12 Address input
BA0, BA1
Bank select address
DQ0 to DQ15 Data-input/output
UDQS, LDQS Input and output data strobe
/CS
Chip select
/RAS
Row address strobe command
/CAS
Column address strobe command
/WE
Write enable
UDM, LDM Input mask
CK
Clock input
/CK
Differential clock input
CKE
Clock enable
VREF
Input reference voltage
⎯ Auto refresh
⎯ Self refresh
VDD
VSS
VDDQ
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
• Ambient temperature range: −40 to +85°C
VSSQ
NC
Ground for DQ circuit
No connection
Document No. E0488E10 (Ver. 1.0) _{This product became EOL in April, 2007.}
Date Published February 2004 (K) Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2004