EDD2504AJTA Datasheet, PDF (1/50 Pages) Elpida Memory – 256M bits DDR SDRAM

PRELIMINARY DATA SHEET
256M bits DDR SDRAM
EEDDDD22550084AAJJTTAA ((3624MM wwoorrddss ×× 84 bbiittss)) _Description
The EDD2504AJ is a 256M bits Double Data Rate
(DDR) SDRAM organized as 16,777,216 words × 4 bits
E× 4 banks. The EDD2508AJ is a 256M bits DDR
SDRAM organized as 8,388,608 words × 8 bits × 4
banks. Read and write operations are performed at the
cross points of the CK and the /CK. This high-speed
data transfer is realized by the 2 bits prefetch-pipelined
O_{architecture. Data strobe (DQS) both for read and}
write are available for high speed and reliable data bus
design. By setting extended mode resistor, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
L ^{They are packaged in standard 66-pin plastic TSOP}
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD VDD 1
NC DQ0 2
VDDQ VDDQ 3
NC NC 4
DQ0 DQ1 5
VSSQ VSSQ 6
NC NC 7
NC DQ2 8
VDDQ VDDQ 9
NC NC 10
DQ1 DQ3 11
VSSQ VSSQ 12
66 VSS VSS
65 DQ7 NC
64 VSSQ VSSQ
63 NC NC
62 DQ6 DQ3
61 VDDQ VDDQ
60 NC NC
59 DQ5 NC
58 VSSQ VSSQ
57 NC NC
56 DQ4 DQ2
55 VDDQ VDDQ
(II).
Features
• 2.5 V power supply: VDDQ = 2.5V ± 0.2V
: VDD = 2.5V ± 0.2V
• Data rate: 333Mbps/266Mbps (max.)
P • Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
r • Data inputs, outputs, and DM are synchronized with
DQS
o _{• 4 internal banks for concurrent operation}
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
d • DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
u _{• Data mask (DM) for write data}
• Auto precharge option for each burst access
• 2.5 V (SSTL_2 compatible) I/O
• Programmable burst length (BL): 2, 4, 8
c _{• Programmable /CAS latency (CL): 2, 2.5}
• Refresh cycles: 8192 refresh cycles/64ms
t ^{⎯ 7.8μs maximum average periodic refresh interval}
NC NC 13
NC NC 14
VDDQ VDDQ 15
NC NC 16
NC NC 17
VDD VDD 18
NC NC 19
NC NC 20
/WE /WE 21
/CAS /CAS 22
/RAS /RAS 23
/CS /CS 24
NC NC 25
BA0 BA0 26
BA1 BA1 27
A10(AP) A10(AP) 28
A0
A0 29
A1
A1 30
A2
A2 31
A3
A3 32
VDD VDD 33
54 NC NC
53 NC NC
52 VSSQ VSSQ
51 DQS DQS
50 NC NC
49 VREF VREF
48 VSS VSS
47 DM DM
46 /CK /CK
45 CK CK
44 CKE CKE
43 NC NC
42 A12 A12
41 A11 A11
40 A9 A9
39 A8 A8
38 A7 A7
37 A6 A6
36 A5 A5
35 A4 A4
34 VSS VSS
A0 to A12
BA0, BA1
DQ0 to DQ7
DQS
/CS
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
X8
X4
(Top view)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
• 2 variations of refresh
VSS
Ground for internal circuit
⎯ Auto refresh
⎯ Self refresh
VDDQ
VSSQ
NC
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0145E50 (Ver. 5.0)
Date Published November 2002 (K) Japan
URL: http://www.elpida.com
This product became EOL in April, 2007.
©Elpida Memory, Inc. 2001-2002