EDD1232ACBH-6B Datasheet, PDF (1/52 Pages) Elpida Memory – 128M bits DDR SDRAM

PRELIMINARY DATA SHEET
128M bits DDR SDRAM
EDD1232ACBH-6B (4M words × 32 bits) _{Specifications}
• Density: 128M bits
• Organization
 1M words × 32 bits × 4 banks
E• Package: 144-ball FBGA
 Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Data rate: 333Mbps (max.)
O• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
 Sequential (2, 4, 8)
L _{ Interleave (2, 4, 8)}
• /CAS Latency (CL): 2.5, 3
• Precharge: auto precharge option for each burst
access
• Driver strength: weak/matched
P ^{• Refresh: auto-refresh, self-refresh}
• Refresh cycles: 4096 cycles/32ms
 Average refresh period: 7.8µs
• Operating ambient temperature range
roduct ^{ TA=0°Cto+70°C}
Features
• ×32 organization
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
Document No. E1550E10 (Ver. 1.0) _{This product became EOL in March, 2010.}
Date Published January 2010 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2010