EDD1216AJBG Datasheet, PDF (1/51 Pages) Elpida Memory – 128M bits DDR SDRAM

PRELIMINARY DATA SHEET
128M bits DDR SDRAM
EDD1216AJBG (8M words × 16 bits) _{Specifications}
• Density: 128M bits
• Organization
 2M words × 16 bits × 4 banks
E• Package: 60-ball FBGA
 Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Data rate: 400Mbps/333Mbps/266Mbps (max.)
O• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
 Sequential (2, 4, 8)
L _{ Interleave (2, 4, 8)}
• /CAS Latency (CL): 2, 2.5, 3
• Precharge: auto precharge option for each burst
access
• Driver strength: normal/weak
P ^{• Refresh: auto-refresh, self-refresh}
• Refresh cycles: 4096 cycles/64ms
 Average refresh period: 15.6µs
• Operating ambient temperature range
r ^{ TA = 0°C to +70°C}
o _Features
• Double-data-rate architecture; two data transfers per
clock cycle
d • The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
u • Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
c ^{• Differential clock inputs (CK and /CK)}
• DLL aligns DQ and DQS transitions with CK
transitions
t ^{• Commands entered on each positive CK edge; data}
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA
123456789
A
VSSQ DQ15 VSS
B
DQ14 VDDQ DQ13
C
DQ12 VSSQ DQ11
D
DQ10 VDDQ DQ9
E
DQ8 VSSQ UDQS
F
VREF VSS UDM
G
CK /CK
H
NC CKE
J
A11 A9
K
A8 A7
L
A6 A5
M
A4 VSS
VDD DQ0 VDDQ
DQ2 VSSQ DQ1
DQ4 VDDQ DQ3
DQ6 VSSQ DQ5
LDQS VDDQ DQ7
LDM VDD NC
/WE /CAS
/RAS /CS
BA1 BA0
A0 A10
(AP)
A2 A1
VDD A3
A0 to A11
BA0, BA1
DQ0 to DQ15
UQQS, LDQS
/CS
/RAS
/CAS
/WE
UDM, LDM
CK
/CK
CKE
VREF
VDD
VSS
(Top view)
Address inputs
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe
Column address strobe
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
and data mask referenced to both edges of DQS
VDDQ
Power for DQ circuit
• Data mask (DM) for write data
VSSQ
NC
Ground for DQ circuit
No connection
Document No. E1154E10 (Ver. 1.0)
Date Published July 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in April, 2010.
Elpida Memory, Inc. 2007