EDD1216AASE Datasheet, PDF (1/49 Pages) Elpida Memory – 128M bits DDR SDRAM (8M words x 16 bits)

PRELIMINARY DATA SHEET
128M bits DDR SDRAM
EDD1216AASE (8M words × 16 bits)
Description
Pin Configurations
The EDD1216AASE is a 128M bits Double Data Rate
(DDR) SDRAM organized as 2,097,154 words × 16 bits
× 4 banks. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in 60-ball FBGA
(µBGA^) package.
Features
• Power supply : VDDQ = 2.5V ± 0.2V
: VDD = 2.5V ± 0.2V
• Data rate: 333Mbps/266Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Programmable output driver strength: normal/weak
• Refresh cycles: 4096 refresh cycles/64ms
 15.6µs maximum average periodic refresh interval
• 2 variations of refresh
 Auto refresh
 Self refresh
• FBGA (µBGA) package with lead free solder
(Sn-Ag-Cu)
/xxx indicates active low signal.
60-ball FBGA ( BGA)
123456789
A
VSSQ DQ15 VSS
B
DQ14 VDDQ DQ13
C
DQ12 VSSQ DQ11
D
DQ10 VDDQ DQ9
E
DQ8 VSSQ UDQS
F
VREF VSS UDM
G
CK /CK
H
NC CKE
J
A11 A9
K
A8 A7
L
A6 A5
M
A4 VSS
VDD DQ0 VDDQ
DQ2 VSSQ DQ1
DQ4 VDDQ DQ3
DQ6 VSSQ DQ5
LDQS VDDQ DQ7
LDM VDD NC
/WE /CAS
/RAS /CS
BA1 BA0
A0 A10
(AP)
A2 A1
VDD A3
A0 to A11
BA0, BA1
DQ0 to DQ15
UQQS/LDQS
/CS
/RAS
/CAS
/WE
UDM/LDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
(Top view)
Address inputs
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe
Column address strobe
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0614E20 (Ver. 2.0)
Date Published March 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005