ECS6432AFCN-A Datasheet, PDF (1/47 Pages) Elpida Memory – 64M bits SDRAM Bare Chip

PRELIMINARY DATA SHEET
64M bits SDRAM Bare Chip
ECS6432AFCN-A (2M words × 32 bits) _{Specifications}
• Density: 64M bits
• Organization
 512K words × 32 bits × 4 banks
E• Package: Bare chip
• Power supply: VDD, VDDQ = 3.3V ± 0.3V
• Clock frequency: 133MHz (max.)
• Four internal banks for concurrent operation
O• Interface: LVTTL
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
 Sequential (1, 2, 4, 8, full page)
 Interleave (1, 2, 4, 8)
L _{• /CAS Latency (CL): 2, 3}
• Precharge: auto precharge operation for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
P ^{ Average refresh period: 15.6µs}
• Operating junction temperature range
roduct ^{ TJ=0°Cto+100°C}
Features
• ×32 organization
• Single pulsed /RAS
• Burst read/write operation and burst read/single write
operation capability
• Byte control by DQM
Document No. E0743E20 (Ver. 2.0) _{This product became EOL in October, 2007.}
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005