ECS1232ABCN-A Datasheet, PDF (1/46 Pages) Elpida Memory – 128M bits SDRAM Bare Chip

DATA SHEET
128M bits SDRAM Bare Chip
ECS1232ABCN-A (4M words × 32 bits) _Description
The ECS1232ABCN is a 128M bits SDRAM organized
as 1,048,576 words × 32 bits × 4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
EOL _{This product is Bare Chip.}
Features
• 3.3V power supply
• Clock frequency: 133MHz (max.)
• Single pulsed /RAS
• ×32 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
⎯ Sequential (BL = 1, 2, 4, 8, full page)
⎯ Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
• Address
⎯ 4K Row address /256 column address
• Refresh cycles
⎯ 4096 refresh cycles/64ms
P • 2 variations of refresh
⎯ Auto refresh
roduct ^{⎯ Selfrefresh}
Document No. E0486E30 (Ver. 3.0)
Date Published September 2004 (K) Japan
URL: http://www.elpida.com
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2004