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ECS1216AACN-A Datasheet, PDF (1/47 Pages) Elpida Memory – 128M bits SDRAM Bare Chip | |||
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PRELIMINARY DATA SHEET
128M bits SDRAM Bare Chip
ECS1216AACN-A (8M words à 16 bits) Specifications
⢠Density: 128M bits
⢠Organization
 2M words à 16 bits à 4 banks
E⢠Package: Bare chip
⢠Power supply: VDD, VDDQ = 3.3V ± 0.3V
⢠Clock frequency: 133MHz (max.)
⢠Four internal banks for concurrent operation
O⢠Interface: LVTTL
⢠Burst lengths (BL): 1, 2, 4, 8, full page
⢠Burst type (BT):
 Sequential (1, 2, 4, 8, full page)
 Interleave (1, 2, 4, 8)
L ⢠/CAS Latency (CL): 2, 3
⢠Precharge: auto precharge operation for each burst
access
⢠Refresh: auto-refresh, self-refresh
⢠Refresh cycles: 4096 cycles/64ms
P  Average refresh period: 15.6µs
⢠Operating junction temperature range
roduct  TJ=0°Cto+90°C
Features
⢠Single pulsed /RAS
⢠Burst read/write operation and burst read/single write
operation capability
⢠Byte control by UDQM and LDQM
Document No. E0572E20 (Ver. 2.0) This Product became EOL in November, 2006.
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
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