EBJ21RE8BAFA Datasheet, PDF (1/20 Pages) Elpida Memory – 2GB Registered DDR3 SDRAM DIMM

DATA SHEET
2GB Registered DDR3 SDRAM DIMM
EBJ21RE8BAFA (256M words × 72 bits, 2 Ranks)
Specifications
• Density: 2GB
• Organization
 256M words × 72 bits, 2 ranks
• Mounting 18 pieces of 1G bits DDR3 SDRAM sealed
in FBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
 PCB height: 30.5mm (max.)
 Lead pitch: 1.0mm
 Lead-free (RoHS compliant)
• Power supply: VDD = 1.5V ± 0.075V
• Data rate: 1333Mbps/1066Mbps/800Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_15
• Burst lengths (BL): 8 and 4 with Burst Chop (BC)
• /CAS Latency (CL): 6, 7, 8, 9
• /CAS write latency (CWL): 5, 6, 7
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles
 Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
 TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die-Termination (ODT) for better signal quality
 Synchronous ODT
 Dynamic ODT
 Asynchronous ODT
• Multi Purpose Register (MPR) for temperature read
out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset
function
• SRT range:
 Normal/extended
 Auto/manual self-refresh
• Programmable Output driver impedance control
• 1 piece of registering clock driver and 1 piece of
serial EEPROM (256 bytes EEPROM) for Presence
Detect (PD).
• Class B temperature sensor functionality with
EEPROM
Document No. E1251E40 (Ver. 4.0)
Date Published December 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007-2008