EBE51UD8ABFV Datasheet, PDF (1/22 Pages) Elpida Memory – 512MB Unbuffered DDR2 SDRAM HYPER DIMM™

PRELIMINARY DATA SHEET
512MB Unbuffered DDR2 SDRAM
HYPER DIMM
EBE51UD8ABFV (64M words × 64 bits, 1 Rank) _Description
The EBE51UD8ABFV is 64M words × 64 bits, 1 rank
EDDR2 SDRAM unbuffered module, mounting 8 pieces
of 512M bits DDR2 SDRAM sealed in FBGA package.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 4 bits prefetch-pipelined
O^{architecture. Data strobe (DQS and /DQS) both for}
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module provides high density
mounting without utilizing surface mount technology.
L _{Decoupling capacitors are mounted beside each FBGA}
on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
Product ^{which may result in electrical defects.}
Features
• 240-pin socket type dual in line memory module
(DIMM)
 PCB height: 30.0mm
 Lead pitch: 1.0mm
 Lead-free
• 1.85V power supply
• Data rate: 667Mbps/600Mbps (max.)
• SSTL_18 compatible I/O
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
(components)
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• 7.8µs average periodic refresh interval
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E0528E12 (Ver. 1.2) _{This product became EOL in April, 2005.}
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2006