EBE51RC4AAFA Datasheet, PDF (1/22 Pages) Elpida Memory – 512MB Registered DDR2 SDRAM DIMM

PRELIMINARY DATA SHEET
512MB Registered DDR2 SDRAM DIMM
EBE51RC4AAFA (64M words × 72 bits, 1 Rank) _Description
The EBE51RC4AAFA is a 64M words × 72 bits, 1 rank
DDR2 SDRAM Module, mounting 18 pieces of DDR2
SDRAM sealed in FBGA package. Read and write
operations are performed at the cross points of the CK
Eand the /CK. This high-speed data transfer is realized
by the 4bits prefetch-pipelined architecture. Data
strobe (DQS and /DQS) both for read and write are
available for high speed and reliable data bus design.
O^{By setting extended mode register, the on-chip Delay}
Locked Loop (DLL) can be set enable or disable. This
module provides high density mounting without utilizing
surface mount technology. Decoupling capacitors are
mounted beside each FBGA on the module board.
L _{Note: Do not push the components or drop the}
modules in order to avoid mechanical defects,
Product ^{which may result in electrical defects.}
Features
• 240-pin socket type dual in line memory module
(DIMM)
 PCB height: 30.0mm
 Lead pitch: 1.0mm
 Lead-free
• 1.8V power supply
• Data rate: 533Mbps/400Mbps (max.)
• 1.8 V (SSTL_18 compatible) I/O
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, data strobe (DQS and /DQS) is
transmitted /received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Four internal banks for concurrent operation
(Component)
• Burst length: 4, 8
• /CAS latency (CL): 3, 4, 5
• Auto precharge option for each burst access
• Auto refresh and self refresh modes
• 7.8µs average periodic refresh interval
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)
Document No. E0471E11 (Ver. 1.1) _{This product became EOL in April, 2005.}
Date Published February 2006 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2006