E910.46 Datasheet, PDF (1/1 Pages) ELMOS Semiconductor AG – EC motor control

BUS IC
DC/DC CONVERTER
MOTOR DRIVER IC
Fan control
ÿ EC motor control
Steppermotor driver
RIPPLE COUNTER
ÿ EC motor control
FEATURES
ÿ High voltage supply in the range VS = 6.0 V to 58 V
ÿ Drive of up to 6 external n-channel Power
FETs (3 high side- and 3 low side switches)
ÿ Programmability of functions and parameters by
SPI µP interface
ÿ Self adjusting driver timing and power FET protection
ÿ High power efficiency
ÿ Low RF emission due to the field programmable
driver technology
ÿ Three current measurement amplifiers and
programmable over current protection
ÿ On chip and external over temperature detection
and protection
ÿ Programmable analog measurement channels
(temperature and motor currents)
ÿ Position detection by BEMF
ÿ Sleep / Wake up mode system
ÿ 5V or 3.3V interface to control device
ÿ Developmentkits available (programmable board
and software with PC Interface)
ÿ – 40°C to + 125°C operating temperature
ÿ PLCC68 package
APPLICATION
ÿ EC or DC motor drive / regulation
ÿ Fan cooler
ÿ Air-conditioning
ÿ Pumps
DESCRIPTION
The IC is a PWM EC brushless motor driver/controller to imple-
ment a motor regulator together with n-channel power FET B6-
configuration and a µC The programmability of parameters (e.g.
threshold values of over current, over temperature, motor fail-
ures, EMC conditions, etc.) can be used to drive motors in a widely
different range. These programmability features and the driver
channel control inputs and allow this chip to act in general motor
regulator applications, too. The special programmable switching
technology (pendingpatent) enables an excellent EMC behavior.
The device works in typical motor regulator systems as physical
interface between a µC or a special controller hardware and the
power FET-motor load configuration. The user has the complete
control over the logical behaviour by software implementation in
the µC. In this way all control/regulation strategies of the motor
can be realised by software development.
BLOCK DIAGRAM
40
VBAT
CVCP
VCP
VDD
CCP
CP1
CP2
MISO
MOSI
SCL
CS
Fail
Wake
x-HI ³
x-LO 3
µC VDS_OVER_xH ³
VDS_OVER_xL ³
VBAT
Charge
Pump
SPI
PFET Monitor
PROG
POS_x ³
SH_x ³
A_CUR_SH_x 3
SIGN_x 3
RREF
IREF
IREF
optional
VDD VDD3 VS
Rmeas (optional)
VCP
T1
T2
T3
slewrate
control
3_{Gx_HI}
prog.
control
3 _{ISENH_x}
S/H
3 _{ISENL_x}
analog
MUX
overcurrent detection
3 PH_x
SP (opt.)
VS
T4
T5
T6
slewrate
control
3 Gx_L0
prog.
VDD
R1
ext. & int.
IP
overtemperature detection
ϑ
ANAMUX
DRIVER IC
I/O IC
SENSOR IC
SENSOR INTERFACE IC
system evaluation chip
E910.46
PINNING
Pin
1
2
3
4
5-7
8
9
10
11-13
14-16
17
18
19
20
21
22
23
24
25-27
28-29
30-31
32-33
34
35
36-38
39-41
42
43
44,46
48
Name
ISENH_A
ISENL_A
DGND
VDD
A_CUR_SH_[C-A]
TP
ANAMUX
IREF
SH_[A-C]
SIGN[A-C]
VDD3
VSSA
CS
SCL
MOSI
MISO
FAIL
WAKE
POS_[A-C]
VDS_OVER_A[H,L]
VDS_OVER_B[H,L]
VDS_OVER_C[H,L]
VDD3
AGND
[A-C]_HI
[A-C]_LO
VS
PGND
GC_LO, GB_LO
GA_LO
Description
Positive current measurement
input, channel A
Negative current measurement
input, channel A
Digital ground
5V supply
Current measurement output,
channel [A-C], S&H
Temperature sensor input
Analog MUX output
Reference current output
Sample and hold control
input, channel [A-C]
Sign of current output, channel [A-C]
3.3 V or 5 V supply of
control interface
Analog ground
Enable signal of SPI
Clock of SPI
Data input of SPI
Data output of SPI
Failure signal, high active
Wake up signal, low active
Position signal of BEMF
detection, channel [A-C]
VDS detection, high/low
side switch, channel A
VDS detection, high/low
side switch, channel B
VDS detection, high/low
side switch, channel C
3.3V or 5V supply of control interface
Analog ground
Ctrl input of HS switch,
channel [A-C], high active
Ctrl input of LS switch,
channel [A-C], high active
12V supply
Power ground
Driver output, gate LS
FET, channel c/b
Driver output, gate LS
power FET, channel A
PACKAGE
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
IREF 10
60 CP1
SH_A 11
59 VPUMP
SH_B 12
58 VDD12P
SH_C 13
57 CP2
SIGNA 14
56 PHA
SIGNB 15
55 GA_HI
SIGNC 16
54 PHB
VDD3 17
53 GB_HI
VSSA 18
52 PHC
CS 19
51 GC_HI
SCL 20
50 SP
MOSI 21
49 n.c.
MISO 22
48 GA_LO
FAIL 23
47 n.c.
WAKE 24
46 GB_LO
POS_A 25
45 n.c.
POS_B 26
44 GC_LO
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AVAILABILITY
Samples
Series
available
tbd.
Pin
Name
50
SP
51
GC_HI
52,54, 56 PHC, PHB, PHA
53
GB_HI
55
GA_HI
57
58,63
59
CP2
VBAT, VS
VPUMP
60
62
64,66
CP1
PGND
ISENH_C, ISENL_C
67-68 ISENH_B, ISENL_B
Description
Star point connection
Driver output, gate HS
power FET, channel C
Phase C-A
Driver output, gate HS
power FET, channel B
Driver output, gate HS
power FET, channel A
Switch capacitor connection
2 of charge pump
12V supply, high voltage supply
Pumped voltage, storage
capacitor connection
Switch capacitor connection
1 of charge pump
Power ground
Pos/Neg current measurement
input, channel C
Pos/Neg current measurement
input, channel B
Note ELMOS Semiconductor AG (below ELMOS) reserves the right to make changes to the product contained in this publication without notice. ELMOS assumes no responsibility for the use of any
circuits described herein, conveys no licence under any patent or other right, and makes no representation that the circuits are free of patent infringement. While the information in this publication
has been checked, no responsibility, however, is assumed for inaccuracies. ELMOS does not recommend the use of any of its products in life support applications where the failure or malfunction of
the product can reasonably be expected to cause failure of a life-support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications.
Copyright © 2005 ELMOS Reproduction, in part or whole, without the prior written consent of ELMOS, is prohibited.
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elmos product catalog june 2005
41