GD25LQ64C Datasheet, PDF (28/62 Pages) ELM Electronics – 64M-bit Serial Flash

GD25LQ64CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
command → 3-byte address on SI → at least 1 byte data on SI→ CS# goes high. The command sequence is
shown in Figure15. If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes
are sent to device, they are correctly programmed at the requested addresses without having any effects on the
other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched
in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1 and BP0) is not executed.
Figure 15. Page Program Sequence Diagram
CS#
SCLK
IO₀
IO₁
IO₂
IO₃
Figure 15a. Page Program Sequence Diagram (QPI)
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Command
02H _{A23-16 A15-8}
20 16 12 8
A7-0
40
Byte1
40
Byte2
40
Byte3
40
Byte255 Byte256
4 04 0
21 17 13 9 5 1 5 1 5 1 5 1
5 15 1
22 18 14 10 6 2 6 2 6 2 6 2
6 26 2
23 19 15 11 7 3 7 3 7 3 7 3
7 37 3
62 - 28
Rev.1.0