GD25Q41BXIGX Datasheet, PDF (16/46 Pages) ELM Electronics – Uniform Sector Dual and Quad Serial Flash

GD25Q41BxIGx Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Figure 4. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
01234567
Command(50H)
SI
SO
High-Z
7.4. Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read
at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles
is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to
the device. It is also possible to read the Status Register continuously. For command code “05H”, the SO will
output Status Register bits S7~S0. The command code “35H”, the SO will output Status Register bits S15~S8.
Figure 5. Read Status Register Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
SI
05H or 35H
SO
High-Z
S7~S0 or S15~S8 out
S7~S0 or S15~S8 out
76543210765432107
MSB
MSB
7.5. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it
can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable
(WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) (01H) command has no effect on S15, S10, S1 and S0 of the Status
Register. CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the
Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write
Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the
Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
To write non-volatile Status Register bits, a standard Write Enable (06H) instruction must previously have
been executed for the device to accept the Write Status Register Instruction. Once write enabled, the instruction
is entered by driving CS# low, sending the instruction code “01H”, and then writing the status register data byte.
46 - 16
Rev.1.1