|
GD25LQ128CXIGX Datasheet, PDF (7/62 Pages) ELM Technology Corporation – 1.8V Uniform Sector Dual and Quad Serial Flash | |||
|
◁ |
GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash
4. DEVICE OPERATION
http://www.elm-tech.com
SPI Mode
Standard SPI
The GD25LQ128C feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select
(CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data
is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25LQ128C supports Dual SPI operation when using the âDual Output Fast Readâ and âDual I/O Fast
Readâ (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two
times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional
I/O pins: IO0 and IO1.
Quad SPI
The GD25LQ128C supports Quad SPI operation when using the âQuad Output Fast Readâ, âQuad I/O
Fast Readâ, âQuad I/O Word Fast Readâ âQuad Page Programâ (6BH, EBH, E7H, 32H) commands. These
commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When
using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and
HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in
Status Register to be set.
QPI
The GD25LQ128C supports Quad Peripheral Interface (QPI) operations only when the device is switched
ftom Standard/Dual/Quad SPI mode to QPI mode using the âEnable the QPI (38H)â command. The QPI
mode utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are
exclusive. Only one mode can be active at any given times. âEnable the QPI (38H)â and âDisable the QPI (FFH)â
commands are used to switch between these two modes. Upon power-up and after software reset using âReset
(99H)â command, the default state of the device is Standard/Dual/Quad SPI mode. The QPI mode requires the
non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesnât stop the operation
of write status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK
signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD
condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD
operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK donât care during the HOLD operation, if CS# drives high
during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the
HOLD# must be at high and then CS# must be at low.
62 - 7
Rev.1.0
|
▷ |