EL4585C Datasheet, PDF (1/16 Pages) Elantec Semiconductor – Horizontal Genlock, 8 FSC

EL4585C
Horizontal Genlock 8 F_SC
Features
 36 MHz general purpose PLL
 8 F_SC timing (Use the EL4584
for 4 F_SC)
 Compatible with EL4583C Sync
Separator
 VCXO Xtal or LC tank
oscillator
 ^k2nS jitter (VCXO)
 User-controlled PLL capture and
lock
 Compatible with NTSC and PAL
TV formats
 8 pre-programmed popular TV
scan rate clock divisors
 Single 5V low current operation
Applications
 Pixel Clock regeneration
 Video compression engine
(MPEG) clock generator
 Video Capture or digitization
 PIP (Picture In Picture) timing
generator
 Text or Graphics overlay timing
Ordering Information
Part No Temp Range Package Outline
EL4585CN b40 C to a85 C 16-Pin DIP MDP0031
EL4585CS b40 C to a85 C 16-Lead SO MDP0027
For 3Fsc and 4Fsc clock frequency operation
see EL4584 datasheet
Demo Board
A demo PCB is available for this
product Request ‘‘EL4584 5 Demo
Board’’
General Description
The EL4585C is a PLL (Phase Lock Loop) sub system designed
for video applications but also suitable for general purpose use
up to 36 MHz In a video application this device generates a
TTL CMOS compatible Pixel Clock (Clk Out) which is a multi-
ple of the TV Horizontal scan rate and phase locked to it
The reference signal is a horizontal sync signal TTL CMOS
format which can be easily derived from an analog composite
video signal with the EL4583 Sync Separator An input signal
to ‘‘coast’’ is provided for applications where periodic distur-
bances are present in the reference video timing such as VTR
head switching The Lock detector output indicates correct lock
The divider ratio is four ratios for NTSC and four similar ratios
for the PAL video timing standards by external selection of
three control pins These four ratios have been selected for com-
mon video applications including 8 F_SC 6 F_SC 27 MHz (CCIR
601 format) and square picture elements used in some worksta-
tion graphics To generate 4 F_SC 3 F_SC 13 5 MHz (CCIR 601
format) etc use the EL4584 which does not have the addition-
al divide by 2 stage of the EL4585
For applications where these frequencies are inappropriate or
for general purpose PLL applications the internal divider can be
by passed and an external divider chain used
FREQUENCIES and DIVISORS
Function
6Fsc
CCIR 601
Square
Divisor
PAL Fosc (MHz)
1702
26 602
1728
27 0
1888
29 5
Divisor
NTSC Fosc (MHz)
1364
21 476
1716
27 0
1560
24 546
CCIR 601 divisors yield 1440 pixels in the active portion of each line for NTSC and PAL
Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL
6Fsc frequencies do not yield integer divisors
Divisor does not include d 2 block
8Fsc
2270
35 468
1820
28 636
Connection Diagram
EL4585 SO P-DIP Packages
4585 – 17
Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ‘‘controlled document’’ Current revisions if any to these
specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation
4585C
1995 Elantec Inc