EC25C256 Datasheet, PDF (8/18 Pages) E-CMOS Corporation – 256Kbits SPI Serial EEPROM

256Kbits SPI Serial EEPROM
EC25C256
Read Lock Status
The Read Lock Status instruction (see Table 3) allows to check if the Identification Page is locked (or not) in
read-only mode. The Read Lock Status sequence is defined with the Chip Select(CS) first driven low. The bits
of the instruction byte and address bytes are then shifted in on Serial Data input (SI). Address bit A10 must be
1, all other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial
Data output (SO). It is at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If Chip Select ( CS )
continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving Chip
Select ( CS ) high (Figure10).
Lock ID
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction
can be accepted, a Write Enable(WREN) instruction must have been executed. The Lock ID instruction is
issued by driving Chip Select (CS) low, sending the instruction code, the address and a data byte on Serial
Data input (SI), and driving Chip Select(CS) high. In the address sent, A10 must be equal to 1, all other
address bits are Don't Care. The data byte sent must be equal to the binary value xxxxxx1x, where x = Don't
Care. Chip Select ( CS ) must be driven high after the rising edge of Serial Clock(SCK) that latches in the
eighth bit of the data byte, and before the next rising edge of Serial Clock(SCK). Otherwise, the Lock ID
instruction is not executed. Driving Chip Select(CS) high at a byte boundary of the input data triggers the self-
timed write cycle whose duration is TWR. The instruction sequence is shown in Figure 11.
The instruction is not accepted, and so not executed, under the following conditions:
— If the Write Enable Latch (WEL) bit has not been set to 1(by previously executing a Write Enable
instruction).
— If Status register bits (BP1,BP0) = (1,1).
— If a write cycle is already in progress.
— If the device has not been deselected, by Chip Select(CS) being driven high, at a byte boundary (after the
eighth bit, b0, of the last data byte that was latched in).
— If the Identification page is locked by the Lock Status bit.
Table 4: Write Protection
WPEN WP
Hardware Write
Protection
0
X
Not Enabled
0
X
Not Enabled
1
0
Enabled
1
0
Enabled
X
1
Not Enabled
X
1
Not Enabled
Note: X = Don't care bit.
WEN Inside Block Outside Block
0
Read-only
Read-only
1
Read-only
Unprotected
0
Read-only
Read-only
1
Read-only
Unprotected
0
Read-only
Read-only
1
Read-only
Unprotected
Status Register
(WPEN, BP1, BP0)
Read-only
Unprotected
Read-only
Read-only
Read-only
Unprotected
Name
AN
Don't Care Bits
Table 5: Address Key
EC25C256
A14-A0
A15
E-CMOS Corp. (www.ecmos.com.tw)
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4J09N-Rev.F001