EC3228 Datasheet, PDF (14/16 Pages) E-CMOS Corporation – High-Performance PWM Controller

High-Performance PWM Controller
EC3228
Application Information(Cont.)
capacitors must be connected between the drain of high-side MOSFET
and the source of low-side MOSFET with very low-impedance PCB
layout.
MOSFET Selection
The application for a notebook battery with a maximum voltage of 24V,
at least a minimum 30V MOSFETs should be used. The design has to
trade off the gate charge with the RDS(ON) of the MOSFET:
For the low-side MOSFET, before it is turned on, the body diode has
been conducting. The low-side MOSFET driver will not charge the miller
capacitor of this MOSFET. In the turning off process of the low-side
MOSFET, the load current will shift to the body diode first. The high
dv/dt of the phase node voltage will charge the miller capacitor through
the low-side MOSFET driver sinking current path. This results in much
less switching loss of the low side MOSFETs. The duty cycle is often very
small in high battery voltage applications, and the low-side MOSFET will
conduct most of the switching cycle; therefore, when using smaller
RDS(ON) of the low-side MOSFET, the converter can reduce power loss.
The gate charge for this MOSFET is usually the secondary consideration.
The high-side MOSFET does not have this zero voltage switching
condition; in addition, because it conducts for less time compared to
the low-side MOSFET, the switching loss tends to be dominant. Priority
should be given to the MOSFETs with less gate charge, so that both the
gate driver loss and switching loss will be minimized.
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reversing transfer capacitance
(CRSS) and maximum output current requirement.
The losses in the MOSFETs have two components: conduction loss and
transition loss. For the high-side and low-side MOSFETs, the losses are
approximately given by the following equations:
Where
IOUT is the load current
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
tSW is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction losses while the high-side
MOSFET includes an additional transition loss. The switching interval,
tSW, is the function of the reverse transfer capacitance CRSS. The
(1+TC) term is a factor in the temperature dependency of the RDS(ON)
and can be extracted from the “RDS(ON) vs. Temperature” curve of the
power MOSFET.
Layout Consideration
In any high switching frequency converter, a correct layout is important
to ensure proper operation of the regulator. With power devices
switching at higher frequency, the resulting current transient will cause
voltage spike across the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition of the PWM
MOSFET. Before turn-off condition, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET and is
freewheeling by the low side MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike during the
switching interval. In general, using short and wide printed circuit traces
should minimize interconnecting impedances and the magnitude of
voltage spike. Besides, signal and power grounds are to be kept
separating and finally combined using ground plane construction or
single point grounding. The best tie-point between the signal ground
and the power ground is at the negative side of the output capacitor on
each channel, where there is less noise. Noisy traces beneath the IC are
not recommended. Below is a checklist for your layout:
·Keep the switching nodes (UGATE, LGATE, BOOT, and PHASE) away from
sensitive small signal nodes since these nodes are fast moving signals.
Therefore, keep traces to these nodes as short as possible and there
should be no other weak signal traces in parallel with theses traces on
any layer.
·The signals going through theses traces have both high dv/dt and high
di/dt with high peak charging and discharging current. The traces from
the gate drivers to the MOSFETs (UGATE and LGATE) should be short
and wide.
·Place the source of the high-side MOSFET and the drain of the low-side
MOSFET as close as possible. Minimizing the impedance with wide
E-CMOS Corp. (www.ecmos.com.tw)
Page 14 of 16
3G15N-Rev.P002