AP7362 Datasheet, PDF (8/13 Pages) Diodes Incorporated – 1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT ULTRA-LOW DROPOUT LINEAR REGULATOR

AP7362
1.5A, LOW QUIESCENT CURRENT, FAST TRANSIENT
ULTRA-LOW DROPOUT LINEAR REGULATOR
Application Information
Input Capacitor
A minimum 2.2μF ceramic capacitor is recommended
between IN and GND pins to decouple input power
supply glitch and noise. The amount of the capacitance
may be increased without limit. Larger input capacitor like
10μF will provide better load transient response. This
input capacitor must be located as close as possible to
the device to assure input stability and reduce noise. For
PCB layout, a wide copper trace is required for both IN
and GND pins. A lower ESR capacitor type allows the
use of less capacitance, while higher ESR type requires
more capacitance.
Output Capacitor
The output capacitor is required to stabilize and help the
transient response of the LDO. The AP7362 is stable with
any type of capacitor, with no limitations on minimum or
maximum ESR. The device is designed to have excellent
transient response for most applications with a small
amount of output capacitance. The device is also stable
with multiple capacitors in parallel, which can be of any
type of value. Additional capacitance helps to reduce
undershoot and overshoot during transient loads. This
capacitor should be placed as close as possible to OUT
and GND pins for optimum performance.
Adjustable Operation
The AP7362 provides output voltage from 0.6V to 5.0V
through external resistor divider as shown below.
V_IN
V_OUT
IN
OUT
AP7362
R1
10µF
Enable _EN
ADJ
GND
R2
10µF
Adjustable Output
The output voltage is calculated by:
VOUT
=
VREF
⎜⎜⎝⎛^{1 +}
R1
R2
⎟⎟⎠⎞
Where V_REF=0.6V (the internal reference voltage)
Rearranging the equation will give the following that is
used for adjusting the output to a particular voltage:
R1
=
R _{2 ⎜⎜⎝⎛}
VOUT
VREF
− 1_{⎟⎟⎠⎞}
To maintain the stability of the internal reference voltage,
R₂ need to be kept smaller than 10kΩ.
No Load Stability
Other than external resistor divider, no minimum load is
required to keep the device stable. The device will remain
stable and regulated in no load condition.
Stability And Phase Margin
Any regulator which operates using a feedback loop must
be compensated in such a way as to ensure adequate
phase margin, which is defined as the difference between
the phase shift and -180 degrees at the frequency where
the loop gain crosses unity (0 dB). For most LDO
regulators, the ESR of the output capacitor is required to
create a zero to add enough phase lead to ensure stable
operation. The AP7362 has an internal compensation
circuit
which
maintains
phase
margin
regardless of the ESR of the output capacitor, any type of
capacitor can be used.
Below two charts show the gain/phase plot of the AP7362
with an output of 1.2V, 10 μF ceramic output capacitor,
delivering 1.5A load current and no load. It can be seen
the phase margin is about 90° (which is very stable).
120
100 PHASE
80
60 _GAIN
40
20
0
-20
-40
-60
-80
-100
V_IN=2.7V
V_OUT=1.2V
I_L=1.5A
C_OUT=10μF CER
-120
100
1k
10k 100k
FREQUENCY(Hz)
140
120
100
80
60
40
20
0
-20
-40
-60
-80
1M
Gain-Bandwidth Plot for 1.5A Load
AP7362
Document number: DS35058 Rev. 2 - 2
8 of 13
www.diodes.com
June 2011
© Diodes Incorporated