PAM8408 Datasheet, PDF (7/11 Pages) Diodes Incorporated – 2x3W STEREO DIFFERENTIAL INPUT CLASS D AUDIO AMPLIFIER WITH MEMORY UP/DOWN VOLUME

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PAM8408
Application Information
Maximum Gain
As shown in block diagram, the PAM8408 has two internal amplifiers stage. The first stage's gain is externally con-figurable, while the second
stage's is internally fixed in a fixed-gain, inverting configuration. The closed-loop gain of the first stage is set by selecting the ratio of Rf to Ri while
the second stage's gain is fixed at 2x. Consequently, the differential gain for the IC is
A_VD=20*log [2*(Rf/Ri)]
The PAM8408 sets maximum Rf=218kΩ and minimum Ri=27kΩ, thus the maximum closed-gain is 24dB.
UP/DOWN Volume Control (DVC)
The PAM8408 features a UP/DOWN volume control which consists of the UP and DOWN pins. An internal clock is used where the clock
frequency value is determined from the following formula:
f_CLK = f_OSC / 2¹³
The oscillator frequency f_OSC value is 250kHz typical with ±20% tolerance. The DVC’s clock frequency is 30Hz (cycle time 33ms) typical.
Volume changes are then effected by toggling either the UP or DOWN pins with a logic low. After a period of 1 cycle pulses with either the UP or
DOWN pins held low, the volume will change to the next specified step, either UP or DOWN, and followed by a short delay. This delay decreases
the longer the line is held low, eventually reaching a delay of zero. The delay allows the user to pull the UP or DOWN terminal low once for one
volume change, or hold down to ramp several volume changes. The delay is optimally configured for push button volume control.
If either the UP or DOWN pin remains low after the first volume transition the volume will change again, but this time after 10 cycles. The followed
transition occurs at 4 cycles for each volume transition. This is intended to provide the user with a volume control that pauses briefly after initial
application, and then slowly increases the rate of volume change as it is continuously applied. This cycle is shown in the timing diagram shown in
figure 1.
There are 32 discrete gain settings ranging from +24dB as maximum to -80dB as minimum. Upon device power on, the amplifier's gain is set to a
default value of 12dB, and the gain will remain when applied a logic low to the SD pin, Volume levels for each step vary and are specified in Gain
Setting table on page 7.
If both the UP and DOWN pins are held high, no volume change will occur. Trigger points for the UP and DOWN pins are at 70% of VDD minimum
for a logic high, and 20% of VDD maximum for a logic low. It is recommended, however, to toggle UP and DOWN between VDD and GND for best
performance.
UP/D N
VOL U ME
L EVEL
1 c y c le
1 0 c y c le s
4 c y c le s
4 c y c le s
Figure 1 Timming Diagram
Shutdown Operation
In order to reduce power consumption while not in use, the PAM8408 contains shutdown circuitry that is used to turn off the amplifier's bias
circuitry. This shutdown feature turns the amplifier off when logic low is placed on the SD pin. By switching the SD pin connected to GND, the
PAM8408 supply current draw will be minimized in idle mode. The SD pin cannot be left floating due to the pull-down internal.
Power Supply decoupling
The PAM8408 is a high performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output THD and PSRR
are as low as possible. Power supply decoupling is affecting low frequency response. Optimum decoupling is achieved by using two capacitors of
different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a
good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1.0µF, placed as close as possible to the device VDD terminal works best.
For filtering lower-frequency noise signals, a larger capacitor of 10µF (ceramic) or greater placed near the audio power amplifier is recommended.
PAM8408
Document number: DS36992 Rev. 1 - 2
7 of 11
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June 2014
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