DDTC123JLP Datasheet, PDF (6/7 Pages) Diodes Incorporated – PRE-BIASED SMALL SIGNAL SURFACE MOUNT 100mA NPN TRANSISTOR

Ordering Information (Note 5)
Device
Marking Code
Packaging
Shipping
DDTC123JLP-7-F
N0
DFN1006-3
3000/Tape & Reel
DDTC143ZLP-7-F
N1
DFN1006-3
3000/Tape & Reel
DDTC114YLP-7-F
N2
DFN1006-3
3000/Tape & Reel
Notes: 5. For Packaging Details, please see below or go to our website at http://www.diodes.com/datasheets/ap02007.pdf.
Marking Information
Date Code Key
Year
Code
Month
Code
2007
U
Jan
Feb
1
2
Nx
Fig. 22
Nx = Product Type Marking Code, see ordering information above
YM = Date Code Marking
Y = Year e.g. U = 2007
M = Month e.g. 9 = September
2008
V
Mar
Apr
3
4
2009
W
May
Jun
5
6
2010
X
Jul
Aug
7
8
2011
Y
Sep
Oct
9
O
2012
Z
Nov
Dec
N
D
Mechanical Details
G
H
A
BC
D
N
L
Fig. 23
DFN1006-3
Dim Min Max Typ
A 0.95 1.075 1.00
B 0.55 0.675 0.60
C 0.45 0.55 0.50
D 0.20 0.30 0.25
K
G 0.47 0.53 0.50
M
H
0 0.05 0.03
K 0.10 0.20 0.15
L 0.20 0.30 0.25
M ⎯ ⎯ 0.35
N ⎯ ⎯ 0.40
All Dimensions in mm
Suggested Pad Layout: (Based on IPC-SM-782)
C
X₁
X G₂
DS30755 Rev. 4 - 2
Y
G₁
Z
Fig. 24
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DFN1006-3
Z
1.1
G1
0.3
G2
0.2
X
0.7
X1
0.25
Y
0.4
C
0.7
All Dimensions in mm
DDTCxxxxLP (R1≠R2 Series)
© Diodes Incorporated