AP7217 Datasheet, PDF (6/7 Pages) Diodes Incorporated – 500mA CMOS LDO

Timing Diagram
t_RP
20mSec-TYP.
1.8V
AP7217
500mA CMOS LDO
V_IN
VD_OUT
EN
VR_OUT
Application Note
Input Capacitor
A 1μF ceramic capacitor is recommended to connect between IN
and GND pins to decouple input power supply glitch and noise.
The amount of the capacitance may be increased without limit. A
lower ESR (Equivalent Series Resistance) capacitor allows the
use of less capacitance, while higher ESR type requires more
capacitance. This input capacitor must be located as close as
possible to the device to assure input stability and less noise. For
PCB layout, a wide copper trace is required for both IN and GND.
Output Capacitor
The output capacitor is required to stabilize and help the transient
response of the LDO. The AP7217 is designed to have excellent
transient response for most applications with a small amount of
output capacitance. The AP7217 is stable with any small ceramic
output capacitors of 1.0μF or higher value, and the temperature
coefficients of X7R or X5R type. Additional capacitance helps to
reduce undershoot and overshoot during transient. For PCB
layout, the output capacitor must be placed as close as possible
to OUT and GND pins, and keep the leads as short as possible.
ENABLE/SHUTDOWN Operation
The AP7217 is turned on by setting the EN pin high, and is turned
off by pulling it low. If this feature is not used, the EN pin should
be tied to IN pin to keep the regulator output on at all time. To
ensure proper operation, the signal source used to drive the EN
pin must be able to swing above and below the specified
turn-on/off voltage thresholds listed in the Electrical
Characteristics section under V_IL and V_IH.
EN=0
EN=1
VROUT
0V
3.3V
VDOUT
Φ
Φ
Current Limit Protection
When output current at OUT pin is higher than current limit
threshold, the current limit protection will be triggered and clamp
the output current to approximately 600mA to prevent
over-current and to protect the regulator from damage due to
overheating.
Short circuit protection
When VRout pin is shorted to GND or VRout voltage is less than
200mV, short circuit protection will be triggered and clamp the
output current to approximately 50mA.
VDOUT (reset output)
---Open-Drain Active-Low reset output---
In general, VD_OUT is pulled up by a resistor (100Kohm) to V_IN.
The AP7217 microprocess (uP) supervisory circuitry asserts a
guaranteed logic-low reset during power-up and power-down.
Reset is asserted asserts when VIN is below the reset threshold
and remain asserted for at least tRP after VIN rises above the reset
threshold.
As long as VIN is lower than the reset threshold, VDOUT remains at
logic "0". When VIN become higher than VTH, a logic "1" is
asserted after a time delay defined by tRP.
AP7217 Rev. 1
6 of 7
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OCTOBER 2007
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