AP7312 Datasheet, PDF (5/18 Pages) Diodes Incorporated – DUAL 150mA LOW QUIESCENT CURRENT FAST TRANSIENT LOW DROPOUT

AP7312
DUAL 150mA LOW QUIESCENT CURRENT FAST
TRANSIENT LOW DROPOUT LINEAR REGULATOR
Electrical Characteristics
(T_A = 25^oC, V_IN = V_OUT +1V, C_IN = 1uF, C_OUT = 1uF, V_EN = V_IN, unless otherwise stated)
Symbol
Parameter
Test Conditions
Min Typ. Max Unit
V_REF
I_ADJ
V_OUT
ADJ Reference Voltage
(Adjustable version)
ADJ Leakage (Adjustable version)
Output Voltage Accuracy
ΔV_OUT /ΔV_IN/V Line Regulation
ΔV_OUT /V_OUT Load Regulation
V_Dropout
I_Q
I_SHDN
I_LEAK
t_ST
Dropout Voltage (Note 4)
Input Quiescent Current (2 channels)
Input Shutdown Current
Input Leakage Current
Start-up Time
PSRR PSRR (Note 5)
I_SHORT Short-circuit Current
I_LIMIT
V_IL
V_IH
I_EN
T_SHDN
T_HYS
θ_JA
Current limit
EN Input Logic Low Voltage
EN Input Logic High Voltage
EN Input Current
Thermal shutdown threshold
Thermal shutdown hysteresis
Thermal Resistance Junction-to-Ambient
I_OUT= 0mA
0.8
V
T_A = -40^oC to 85^oC,
I_OUT = 10% of I_OUT-Max
V_IN = (V_OUT +1V) to V_IN-Max,
V_EN = V_IN, I_OUT = 1mA
V_IN = (V_OUT +1V) to V_IN-Max,
I_OUT = 1mA to 150mA
0.1 1 μA
-2
2%
0.01 0.20 %/V
-0.6
0.6 %
V_OUT < 2.5V, I_OUT = 150mA
V_OUT ≥ 2.5V, I_OUT = 150mA
200 300
mV
150 200
V_EN = V_IN, I_OUT = 0mA
60 80 μA
V_EN = 0V, I_OUT = 0mA
0.1 1 μA
V_EN = 0V, OUT grounded
0.1 1 μA
V_EN = 0V to 2.0V in 1μs,
I_OUT = 150mA
150
μs
V_IN = [V_OUT +1V]V_DC + 0.5V_ppAC, f =
1kHz, I_OUT = 50mA
60
65
dB
V_IN = V_IN-Min to V_IN-Max,
V_OUT = 1/4 target V_OUT
60
mA
V_IN = V_IN-Min to V_IN-Max,
V_OUT/R_OUT = 0.6A
200 300
mA
V_IN = V_IN-Min to V_IN-Max
0.4 V
V_IN = V_IN-Min to V_IN-Max
1.4
V
V_IN = 0V or V_IN-Max
-1
1 μA
165
°C
30
°C
SOT26 (Note 6)
DFN2018-6 (Note 7)
140
o_C/W
60
Notes:
4. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops 2% below its nominal value.
5. This specification is guaranteed by design.
6. Test condition for SOT26: Device mounted on FR-4 substrate PC board, with minimum recommended pad layout
7. Test condition for DFN2018-6: Device mounted on FR-4 2-layer board,2oz copper, with minimum recommended pad on top layer and 3 vias to
bottom layer.
AP7312
Document number: DS35133 Rev. 1 - 2
5 of 18
www.diodes.com
December 2010
© Diodes Incorporated