DMN63D1LDW Datasheet, PDF (4/6 Pages) Diodes Incorporated – DUAL N-CHANNEL ENHANCEMENT MODE MOSFET

5
V_GS= 10.0V
4
3
150℃
85℃
125℃
2
1
0
25℃
-55℃
0.001
0.01
0.1
1
I_D, DRAIN-SOURCE CURRENT (A)
Figure 7. Static Drain-Source On-Resistance vs. Drain
Current
1
V_GS=0V
0.1
T_J=125℃
0.01
T_J=150℃
T_J=85℃
T_J=25℃
0.001
0
T_J=-55℃
0.5
1
1.5
V_SD, SOURCE-DRAIN VOLTAGE (V)
Figure 9. Reverse Drain Current
10
R_DS(ON) Limited
P_W=1ms
1
P_W=100μs
2
T_J=25℃
1.8
DMN63D1LDW
1.6
1.4
I_D=300mA
1.2
I_D=150mA
1
2 3 4 5 6 7 8 9 10
V_GS, GATE-SOURCE VOLTAGE (V)
Figure 8. Static Drain-Source On-Resistance vs. Gate-
Source Voltage
50
f=1MHz
45
40
35
C_iss
30
25
20
15
10
C_rss
C_oss
5
0
0
5
10
15
20
25
30
V_DS, DRAIN-SOURCE VOLTAGE (V)
Figure 10. Typical Junction Capacitance
0.1
P_W=10ms
P_W=100ms
0.01
0.001
T_J(MAX)=150℃
T_A=25℃
Single Pulse
DUT on 1*MRP board
V_GS=10V
P_W=1s
P_W=10s
DC
0.1
1
10
100
V_DS, DRAIN-SOURCE VOLTAGE (V)
Figure 11. SOA, Safe Operation Area
DMN63D1LDW
Document number: DS38033 Rev. 1 - 2
4 of 6
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July 2015
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