ZXLD1101 Datasheet, PDF (3/16 Pages) Zetex Semiconductors – ADJUSTABLE LED DRIVER WITH INTERNAL SWITCH IN TSOT23-5

ZXLD1101
ELECTRICAL CHARACTERISTICS (at V_IN = 3V, T_amb = 25°C unless otherwise stated⁽¹⁾)
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V_IN
Input voltage
I_IN
Supply current
Quiescent
V_EN = V_IN, I_LX = 0,
Output not switching
2.5
5.5
V
60 100 ␮A
Shutdown
V_FB
FB pin control voltage
I_FB
FB pin input current
f_LX
Operating frequency
T_OFF
T_ON
I_LXpk
LX output 'OFF' time
LX output 'ON' time ⁽²⁾
Switch peak current limit
R_LX
I_LX(leak)
V_OUT
V_ENH
V_ENL
I_ENL
I_ENH
T_EN(hold)
Switch 'On' resistance
Switch leakage current
Controller output voltage
EN pin High level Input voltage
EN pin Low level Input voltage
EN pin Low level input current
EN pin High level input current
EN pin turn off delay ⁽³⁾
V_EN = 0V
90.5
L=10␮H, V_OUT =10V,
I_OUT=20mA
350
L=10␮H, V_OUT =10V,
I_OUT=20mA
V_LX =20V
Normal operation
Device active
1.5
Device in shutdown
V_EN =0V
V_EN =V_IN
V_EN switched from high
to low
500 nA
109.5 mV
100 nA
0.35 1 MHz
500
ns
5
µs
320
mA
1.5
⍀
1
µA
28
V
V_IN
V
0.4 V
-100 nA
1
␮A
120
µs
∆T/T
f_LPF
PWM duty cycle range at ‘EN’ input for
filtered PWM control ⁽⁴⁾
Internal PWM low pass filter cut-off
frequency
10kHz < f < 100kHz,
V_ENH =V_IN
20
100 %
4
kHz
A_LPF
∆T/T
Filter attenuation
PWM duty cycle range at ‘EN’ input for
‘gated’ output current control ⁽⁵⁾
f=30kHz
f < 1kHz, V_ENH =V_IN
52.5
dB
0
100 %
NOTES:
(1) Production testing of the device is performed at 25°C. Functional operation of the device over a -40°C to +85°C temperature range is
guaranteed by design, characterisation and process control.
(2) Nominal 'on' time (TONnom) is defined by the input voltage (VIN), coil inductance (L) and peak current (ILXpkdc) according to the expression:
TONnom = {ILX(pkdc) x L/VIN} +200ns.
(3) This is the time for which the device remains active after the EN pin has been asserted low. This delay is necessary to allow the output to be
maintained during dc PWM mode operation.
(4) The minimum PWM signal frequency during this mode of operation is to ensure that the device remains active during PWM control. This
provides a continuous dc output current. For lower frequencies, the device will be gated 'on' and 'off' during PWM control.
(5) The maximum PWM signal frequency during this mode of operation should be kept as low as possible to minimise errors due to the turn-off
delay of the device (see Enable pin turn-off delay).
ISSUE 4 - JULY 2004
3
SEMICONDUCTORS