74HCT164 Datasheet, PDF (3/10 Pages) Diodes Incorporated – 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

74HCT164
Logic Diagram
DSA ¹
DSB ²
CP ⁸
MR ⁹
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
C
C
C
C
C
C
C
C
R
R
R
R
R
R
R
R
3
4
5
6
10
11
12
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Timing Diagram
MR
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
CP
DSA
DSB
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
unknown
unknown
unknown
unknown
unknown
unknown
unknown
unknown
Reset
All Q=0
Reset
All Q=0
Notes:
5. All Q values are reset to LOW when MR goes low. MR is asynchronous and overrides all other signals.
6. Serial data supplied at DSA and DSB is ANDED and transferred to Q0 on positive edge of CP.
74HCT164
Document number: DS36280 Rev. 2 - 2
3 of 10
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August 2015
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