74HC594 Datasheet, PDF (3/10 Pages) NXP Semiconductors – 8-bit shift register with output register

74HC594
Functional Description and Timing Diagram
SHR
L
X
H
H
H
Control
STR
X
L
X
H
H
SHCP
X
X

X

STCP
X
X
L


Input
DS
X
X
H or L
X
H or L
Output
Q7S
L
NC
Q6S
NC
Q6S
Qn
NC
L
NC
Qs
QnS
Function
Clear Shift Register
Clear Storage Register
Loads DS into shift register stage 0. All Q_S shifted
Contents of shift register moved to starge register all Q_S -> Q_N
Shift Register one pulse count ahead of storage register.
H=HIGH voltage state
L=LOW voltage state
=LOW to HIGH transition
X= don’t care – high or low (not floating)
NC= No change
SHCP
DS
STCP
SHR
STR
Q0
Q1
Q6
Q7
Q7S
Absolute Maximum Ratings (Note 4) (@T_A = +25°C, unless otherwise specified.)
Symbol
ESD HBM
ESD CDM
ESD MM
Description
Human Body Model ESD Protection
Charged Device Model ESD Protection
Machine Model ESD Protection
Rating
Unit
2
KV
1
KV
200
V
V_CC
Supply Voltage Range
V_I
Input Voltage Range
V_o
Voltage applied to output in high or low state
I_IK
Input Clamp Current V_I < -0.5V
I_IK
Input Clamp Current VI > Vcc +0.5V
I_OK
Output Clamp Current V_O <-0.5V
I_OK
Output Clamp Current V_O > V_CC + 0.5V
I_O
Continuous output current
Q7 standard output
Qn bus driver outputs
-0.5 to +7.0
V
-0.5 to +7.0
V
-0.3 to V_CC +0.5
V
-20
mA
20
mA
-20
mA
20
mA
±25
mA
±35
mA
I_CC
I_GND
T_J
T_STG
P_TOT
Continuous current through Vcc
Continuous current through GND
Operating Junction Temperature
Storage Temperature
Total Power Dissipation
70
mA
-70
mA
-40 to +150
°C
-65 to +150
°C
500
mW
Note:
4. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device operation should be
within recommend values.
74AHC594
Document number: DS35484 Rev. 3 - 2
3 of 10
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June 2013
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