DT1042-04SO Datasheet, PDF (2/5 Pages) Diodes Incorporated – 4 CHANNEL LOW CAPACITANCE TVS DIODE ARRAY

Maximum Ratings (@T_A = +25°C, unless otherwise specified.)
Characteristic
Peak Pulse Current, per IEC 61000-4-5
Peak Pulse Power, per IEC 61000-4-5
Operating Voltage (DC)
ESD Protection – Contact Discharge, per IEC 61000-4-2
ESD Protection – Air Discharge, per IEC 61000-4-2
Operating Temperature
Storage Temperature
Symbol
I_{PP_I/O}
P_{PP_I/O}
V_DC
V_{ESD_I/O}
V_{ESD_I/O}
T_OP
T_STG
DT1042-04SO
Value
±6
55
5.5
±16
+27/-19
-55 to +85
-55 to +150
Unit
A
W
V
kV
kV
°C
°C
Conditions
I/O to V_SS, 8/20 μs
I/O to V_SS, 8/20 μs
I/O to V_SS
I/O to V_SS
I/O to V_SS
—
—
Thermal Characteristics
Characteristic
Power Dissipation Typical (Note 5)
Thermal Resistance, Junction to Ambient Typical (Note 5)
Symbol
P_D
R_θJA
Value
300
417
Unit
mW
°C/W
Electrical Characteristics (@T_A = +25°C, unless otherwise specified.)
Characteristic
Reverse Working Voltage
Reverse Current (Note 6)
Reverse Current (Note 6)
Reverse Breakdown Voltage
Forward Clamping Voltage
Reverse Clamping Voltage(Note 7)
ESD Clamping Voltage
Dynamic Resistance
Channel Input Capacitance
Symbol
Min
VRWM
—
I_{R(Vcc to Vss)}
—
I_{R(IO to Vss)}
—
VBR
6.2
V_F
-1.0
V_{C_Vcc}
—
V_{C_I/O}
—
V_{ESD_Vcc}
—
V_{ESD_I/O}
—
R_{DIF_Vcc}
—
R_{DIF_I/O}
—
C_{I/O to} V_SS
—
Typ
—
—
—
—
-0.8
6.3
7.7
6.8
9
0.1
0.25
0.65
Max
5.0
1.0
0.5
—
—
—
9
—
—
—
—
0.8
Unit
V
μA
μA
V
V
V
V
V
V
Ω
Ω
pF
Test Conditions
V_CC to V_SS
V_R = V_RWM = 5V, V_CC to V_SS
V_R = V_RWM = 5V, any I/O to V_SS
I_R = 1mA, V_CC to V_SS
I_F = -15mA, V_CC to V_SS
I_PP = 9A, V_CC to V_SS, 8/20 μs
I_PP = 6A, I/O to V_SS, 8/20 μs
TLP, 10A, tp = 100 ns, V_CC to V_SS, per Fig. 8
TLP, 10A, tp = 100 ns, I/O to V_SS, per Fig. 8
TLP, 10A, tp = 100 ns, V_CC to V_SS
TLP, 10A, tp = 100 ns, I/O to V_SS
V_R = 2.5V, V_CC = 5V, f = 1MHz
Variation of Channel Input Capacitance
C_I/O
—
0.02
—
pF
V_CC = 5V, V_SS = 0V, I/O = 2.5V, f =1MHz,
T=+25°C , I/O_x to V_SS – I/O_y to V_SS
Notes:
5. Device mounted on Polymide PCB pad layout (2oz copper) as shown on Diodes Inc. suggested pad layout AP02001, which can be found on our website
at http://www.diodes.com.
6. Short duration pulse test used to minimize self-heating effect.
7. Clamping voltage value is based on an 8x20µs peak pulse current (I_pp) waveform.
DT1042-04SO
Document number: DS36292 Rev. 2 - 2
2 of 5
www.diodes.com
September 2013
© Diodes Incorporated