AP7175 Datasheet, PDF (2/14 Pages) Diodes Incorporated – The AP7175 is a 3.0A ultra low-dropout (LDO) linear regulator that features an enable input and a power-good output.

AP7175
Pin Descriptions
Pin
Name
GND
FB
V_OUT
V_IN
V_CNTL
PG
EN
PAD
Pin Number
SO-8EP MSOP-8EP
1
1
2
2
3/4
3/4
5
5
6
6
7
7
8
8
EP
EP
Function
Ground
Feedback to set the output voltage via an external resistor divider between V_OUT and GND.
Power Output Pin. Connect at least 10µF capacitor to this pin to improve transient response and
required for stability. When the part is disabled the output is discharged via an internal pull-low
MOSFET.
Power Input Pin for current supply. Connect a decoupling capacitor (≥10µF) as close as possible to
the pin for noise filtering.
BIAS supply for the controller, recommended 5V. Connect a decoupling capacitor (≥1µF) as close
as possible to the pin for noise filtering.
Power Good output open drain to indicate the status of V_OUT via monitoring the FB pin. This pin is
pulled low when the voltage is outside the limits, during thermal shutdown and if either V_CNTL or V_IN
go below their thresholds.
Enable pin. Driving this pin low will disable the part. When left floating an internal current source will
pull this pin high and enable it.
Exposed pad connect this to V_IN for good thermal conductivity.
Functional Block Diagram
AP7175
Document number: DS35606 Rev. 3 - 2
2 of 14
www.diodes.com
December 2012
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