74AUP2G14 Datasheet, PDF (2/12 Pages) NXP Semiconductors – Low-power dual Schmitt trigger inverter

Ordering Information
74 AUP2G 14 XXX -7
74AUP2G14
Logic Device
74 : Logic Prefix
AUP : 0.8 to 3.6 V
Logic Family
2G : Dual Gate
Function
14: Inverter with
Schmitt Trigger
Input
Package
DW : SOT363
FW3 : X2-DFN0910-6
FW4 : X2-DFN1010-6
FZ4 : X2- DFN1410-6
Packing
-7 : 7” Tape & Reel
Device
74AUP2G14DW-7
74AUP2G14FW3-7
74AUP2G14FW4-7
74AUP2G14FZ4-7
Package
Code
DW
Package
(Notes 4 & 5)
SOT363
FW3
X2-DFN0910-6
FW4
X2-DFN1010-6
FZ4
X2-DFN1410-6
Package
Size
2.0mm X 2.0mm X 1.1mm
0.65 mm lead pitch
0.9mm X 1.0mm X 0.35mm
0.35 mm pad pitch
1.0mm X 1.0mm X 0.4mm
0.35 mm pad pitch
1.4mm X 1.0mm X 0.4mm
0.5 mm pad pitch
7” Tape and Reel
Quantity
Part Number Suffix
3000/Tape & Reel
-7
5000/Tape & Reel
-7
5000/Tape & Reel
-7
5000/Tape & Reel
-7
Notes:
4. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at
http://www.diodes.com/datasheets/ap02001.pdf.
5. The taping orientation is located on our website at http://www.diodes.com/datasheets/ap02007.pdf
Pin Descriptions
Pin Name
1A
GND
2A
2Y
V_CC
1Y
Pin NO
1
2
3
4
5
6
Function
Data Input
Ground
Data Input
Data Output
Supply Voltage
Data Output
Logic Diagram
Function Table Diagram
Inputs
nA
H
L
Output
nY
L
H
74AUP2G14
Document number: DS35512 Rev. 4 - 2
2 of 12
www.diodes.com
May 2014
© Diodes Incorporated