ZVP4105A Datasheet, PDF (1/1 Pages) Zetex Semiconductors – P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

P-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 50 Volt V_DS
* R_DS(on)=10Ω
* Low threshold
ZVP4105A
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at T_amb=25°C
Pulsed Drain Current
Gate Source Voltage
Power Dissipation at T_amb=25°C
Operating and Storage Temperature Range
SYMBOL
V_DS
I_D
I_DM
V_GS
P_tot
T_j:T_stg
D
G
S
E-Line
TO92 Compatible
VALUE
-50
-175
-520
± 20
625
-55 to +150
UNIT
V
mA
mA
V
mW
°C
ELECTRICAL CHARACTERISTICS (at T_amb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BV_DSS -50
V
I_D=-0.25mA, V_GS=0V
Gate-Source Threshold
Voltage
V_GS(th) -0.8 -2.0 V
ID=-1mA, V_DS= V_GS
Gate-Body Leakage
I_GSS
Zero Gate Voltage Drain
I_DSS
Current
Static Drain-Source On-State R_DS(on)
Resistance (1)
10 nA
-15 µA
-60 µA
-100 nA
10 Ω
V_GS=± 20V, V_DS=0V
V_DS=-50V, V_GS=0V
V_DS=-50V, V_GS=0V, T=125°C(2)
V_DS=-25V, V_GS=0V
V_GS=-5V,I_D=-100mA
Forward Transconductance g_fs
50
(1)(2)
mS V_DS=-25V,I_D=-100mA
Input Capacitance (2)(4)
C_iss
Common Source Output
C_oss
Capacitance (2)(4)
40 pF
15 pF V_DS=-25V, V_GS=0V, f=1MHz
Reverse Transfer
C_rss
Capacitance (2)(4)
6
pF
Turn-On Delay Time (2)(3)(4)
Rise Time (2)(3)(4)
Turn-Off Delay Time (2)(3)(4)
Fall Time (2)(3)(4)
t_d(on)
t_r
t_d(off)
t_f
10 ns
10
ns
V_DD≈-30V, I_D=-270mA
18 ns
25 ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2%
(2) Sample test.
(3) Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator
3-435
(
4
)