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ZVP3310FTA Datasheet, PDF (1/2 Pages) Diodes Incorporated – SOT23 P-CHANNEL ENHANCEMENT SOT23 P-CHANNEL ENHANCEMENT
SOT23 P-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 3 – OCTOBER 1995 7
FEATURES
* 100 Volt VDS
* RDS(on)=20Ω
COMPLEMENTARY TYPE - ZVN3310F
PARTMARKING DETAIL - MR
ZVP3310F
S
D
G
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
SYMBOL
VALUE
UNIT
Drain-Source Voltage
VDS
-100
V
Continuous Drain Current at Tamb=25°C
ID
75
mA
Pulsed Drain Current
IDM
-1.2
A
Gate Source Voltage
VGS
± 20
V
Power Dissipation at Tamb=25°C
Ptot
330
mW
Operating and Storage Temperature Range Tj:Tstg
-55 to +150
°C
ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BVDSS -100
V
ID=-1mA, VGS=0V
Gate-Source Threshold
Voltage
VGS(th) -1.5 -3.5 V
ID=-1mA, VDS= VGS
Gate-Body Leakage
IGSS
-20 nA VGS=± 20V, VDS=0V
Zero Gate Voltage Drain
IDSS
Current
-1
µA VDS=-100V, VGS=0
-50 µA VDS=-80V, VGS=0V, T=125°C(2)
On-State Drain Current(1)
ID(on)
-300
mA VDS=-25 V, VGS=-10V
Static Drain-Source On-State RDS(on)
Resistance (1)
20 Ω
VGS=-10V, ID=-150mA
Forward Transconductance gfs
50
(1)(2)
mS VDS=-25V, ID=-150mA
Input Capacitance (2)
Ciss
Common Source Output
Coss
Capacitance (2)
50 pF
15 pF VDS=-25V, VGS=0V, f=1MHz
Reverse Transfer
Crss
5
pF
Capacitance (2)
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
td(on)
tr
td(off)
tf
8
ns
8
ns
VDD≈-25V, ID=-150mA
8
ns
8
ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sample test.
(3) Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator
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