ZVP3310A_15 Datasheet, PDF (1/3 Pages) Diodes Incorporated – P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

P-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 100 Volt V_DS
* R_DS(on)=20Ω
ZVP3310A
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at T_amb=25°C
Pulsed Drain Current
Gate Source Voltage
Power Dissipation at T_amb=25°C
Operating and Storage Temperature Range
SYMBOL
V_DS
I_D
I_DM
V_GS
P_tot
T_j:T_stg
D
G
S
E-Line
TO92 Compatible
VALUE
-100
-140
-1.2
± 20
625
-55 to +150
UNIT
V
mA
A
V
mW
°C
ELECTRICAL CHARACTERISTICS (at T_amb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BV_DSS -100
V
I_D=-1mA, V_GS=0V
Gate-Source Threshold
Voltage
V_GS(th) -1.5 -3.5 V
ID=-1mA, V_DS= V_GS
Gate-Body Leakage
I_GSS
20 nA V_GS=± 20V, V_DS=0V
Zero Gate Voltage Drain
I_DSS
Current
-1
µA V_DS=-100V, V_GS=0
-50 µA V_DS=-80V, V_GS=0V, T=125°C(2)
On-State Drain Current(1)
I_D(on)
-300
mA V_DS=-25 V, V_GS=-10V
Static Drain-Source On-State R_DS(on)
Resistance (1)
20 Ω
V_GS=-10V,I_D=-150mA
Forward Transconductance g_fs
50
(1)(2)
mS V_DS=-25V,I_D=-150mA
Input Capacitance (2)
C_iss
Common Source Output
C_oss
Capacitance (2)
50 pF
15 pF V_DS=-25V, V_GS=0V, f=1MHz
Reverse Transfer
C_rss
5
pF
Capacitance (2)
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
t_d(on)
t_r
t_d(off)
t_f
8
ns
8
ns
V_DD≈-25V, I_D=-150mA
8
ns
8
ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2%
(2) Sample test.
(
3-432
3
)
Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator