ZVNL110G Datasheet, PDF (1/1 Pages) Zetex Semiconductors – N-CHANNEL ENHANCEMENT MODE LOW THRESHOLD VERTICAL DMOS FET

SOT223 N-CHANNEL ENHANCEMENT MODE
LOW THRESHOLD VERTICAL DMOS FET
ISSUE 2 - FEBRUARY 1996 7
FEATURES
* LOW R_DS(ON) - 3Ω
PARTMARKING DETAIL - ZVNL110
ZVNL110G
D
S
D
G
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
SYMBOL
VALUE
UNIT
Drain-Source Voltage
V_DS
100
V
Continuous Drain Current at T_amb=25°C
I_D
600
mA
Pulsed Drain Current
I_DM
6
A
Gate-Source Voltage
V_GS
± 20
V
Power Dissipation at T_amb=25°C
P_tot
2
W
Operating and Storage Temperature Range T_j:T_stg
-55 to +150
°C
ELECTRICAL CHARACTERISTICS (at T_amb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BV_DSS 100
V
I_D=1mA, V_GS=0V
Gate-Source Threshold Voltage V_GS(th)
Gate-Body Leakage
I_GSS
Zero Gate Voltage Drain
I_DSS
Current
On-State Drain Current(1)
Static Drain-Source On-State
Resistance (1)
I_D(on)
R_DS(on)
Forward Transconductance(1)(2) g_fs
Input Capacitance (2)
C_iss
Common Source Output
Capacitance (2)
C_oss
0.75 1.5
100
10
100
750
4.5
3.0
225
75
25
V
I_D=1mA, V_DS= V_GS
nA V_GS=± 20V, V_DS=0V
µA V_DS=100V, V_GS=0V
µA V_DS=80V, V_GS=0V, T=125°C(2)
mA V_DS=25V, V_GS=5V
Ω
V_GS=5V, I_D=250mA
Ω
V_GS=10V, I_D=500mA
mS V_DS=25V, I_D=500mA
pF
pF V_DS=25V, V_GS=0V, f=1MHz
Reverse Transfer Capacitance (2) C_rss
Turn-On Delay Time (2)(3)
t_d(on)
Rise Time (2)(3)
t_r
Turn-Off Delay Time (2)(3)
t_d(off)
Fall Time (2)(3)
t_f
8
pF
7
ns
12
ns
V_DD≈25V, I_D=1A, V_GS =10V
15
ns
13
ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sample test.
(3) Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator
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